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| e 6/26/97 9:25 am 24329204.doc intel confidential (until publication date) june 1997 order number: 243292-004 maximum operating frequency 133 mhz 150 mhz 166 mhz n support for mmx? technology n compatible with large software base ? ms-dos*, windows*, os/2*, unix* n 32-bit cpu with 64-bit data bus n superscalar architecture ? enhanced pipelines ? two pipelined integer units capable of 2 instructions/clock ? pipelined mmx unit ? pipelined floating-point unit n separate code and data caches ? 16-kbyte code, 16-kbyte write back data ? mesi cache protocol n low voltage cmos silicon technology n 4-mbyte pages for increased tlb hit rate n advanced design features ? deeper write buffers ? enhanced branch prediction feature ? virtual mode extensions n ieee 1149.1 boundary scan n voltage reduction technology ? 2.45 v cc for core supply n internal error detection features n power management features ? system management mode ? clock control n fractional bus operation ? 133-mhz core/66-mhz bus ? 150-mhz core/60-mhz bus ? 166-mhz core/66-mhz bus the mobile pentium ? processor with mmx? technology extends the mobile pentium processor family, providing performance needed for notebook applications. the mobile pentium processor with mmx technology is compatible with the entire installed base of applications for ms-dos*, windows*, os/2*, and unix* and is the first microprocessor to support intel mmx technology. furthermore, the mobile pentium processor with mmx technology has superscalar architecture which can execute two instructions per clock cycle, and enhanced branch prediction and separate caches also increase performance. the pipelined floating-point unit delivers workstation level performance. separate code and data caches reduce cache conflicts while remaining software transparent. the mobile pentium processor with mmx technology has 4.5 million transistors and is built on intel's enhanced 3.3v cmos silicon technology and has full sl enhanced power management features, including system management mode (smm) and clock control. the additional sl enhanced features, 2.45v core operation along with 3.3v i/o buffer operation, and the option of the tcp, which are not available in the desktop version, make the mobile pentium processor with mmx technology ideal for enabling mobile mmx technology designs. the mobile pentium processor with mmx technology may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are available upon request. mobile pentium? processor with mmx? technology
mobile pentium ? processor with mmx? technology e 2 6/26/97 9:25 am 24329204.doc intel confidential (until publication date) information in this document is provided in connection with intel products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intels terms and conditions of sale for such products, intel assumes no liab ility whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liab ility or warranties relating to fitness for a particular purpose, merc hantab ility, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, or life sustaining applications. designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." intel reserves these for future definition and shall have no responsib ility whatsoever for conflicts or incompatibilities arising from future changes to them. intel retains the right to make changes to specifications and product descriptions at any time, without notice. the mobile pentium processor with mmx technology may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are available on request. *third-party brands and names are the property of their respective owners. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product order. copies of documents which have an ordering number and are referenced in this document, or other intel literature, may be obtained from: intel corporation p.o. box 7641 mt. prospect, il 60056-7641 or call 1-800-879-4683 copyright ? intel corporation 1993, 1996, 1997 mobile pentium ? processor with mmx? technology 3 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) contents page page 1.0. microprocessor architecture overview ................................ .................... 4 2.0. microprocessor architecture overview ................................ .................... 4 2.1. mobile pentium ? processor family architecture ................................ ................ 5 2.2. mobile pentium ? processor with mmx tm technology ................................ ................. 7 2.3.1. full support for intel mmx tm technology ................................ ........... 7 2.3.2. doubled code and data caches to 16k each ................................ ..................... 7 2.3.3. improved branch prediction .................. 7 2.3.4. enhanced pipeline ................................ 8 3.0. mobile pentium ? processor with mmx? technology pinout ................... 8 3.1. mobile differences from desktop ................ 8 3.2. tcp pinout and pin descriptions ................ 9 3.2.1. tcp mobile pentium ? processor with mmx? technology pinout ..................... 9 3.2.2. tcp mobile pentium ? processor with mmx? technology pin cross reference ................................ ..... 10 3.3. ppga package ................................ ......... 17 3.3.1. ppga pin diagrams ........................... 17 3.3.2 ppga mobile pentium? processor with mmx? technology pin cross reference ................................ ..... 19 3.4. design notes ................................ ............ 22 3.5. quick pin reference ................................ . 22 3.6. bus frequency ................................ ......... 30 3.7. pin reference tables ................................ 31 3.8. pin grouping according to function .......... 34 4.0. electrical specifications ................ 35 4.1. maximum ratings ................................ ..... 35 4.2. dc specifications ................................ ...... 35 4.2.1. power sequencing ..................... 35 4.3. ac specifications ................................ ...... 38 4.3.1. power and ground .................... 38 4.3.2. decoupling recommendations 38 4.3.3. connection specifications ..... 39 4.3.4. ac timings for a 60-mhz bus .... 39 4.3.5. ac timings for a 66-mhz bus .... 45 4.4. i/o buffer models ................................ ...... 54 4.4.1. buffer model parameters ...... 57 4.4.2. signal quality specifications 60 clock signal measurement methodology ............................... 64 5.0. mechanical specifications ............... 66 5.1. tcp mechanical diagrams ....................... 67 5.2. plastic pin grid array (ppga) ................... 73 6.0. thermal specifications ..................... 75 6.1. measuring thermal values for tcp .......... 75 6.1.1. tcp thermal equations ..................... 75 6.1.2. tcp thermal characteristics ............. 75 6.1.3. tcp pc board enhancements ........... 75 6.1.3.1. tcp standard test board configuration ............................. 76 6.2. measuring thermal values for ppga ...... 77 6.2.1. thermal equations and data . 78 mobile pentium ? processor with mmx? technology 4 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) 1. 0. microprocessor architecture overview the mobile pentium ? processor with mmx? technology is functionally similar to the mobile pentium processor with voltage reduction technology (75-150) with the following differences: voltage supplies, maximum bus and core frequency and performance. this processor is socket compatible with the mobile pentium processor voltage reduction technology (75-150) making it possible to design a flexible motherboard that supports both the mobile pentium processor (75-150) and the mobile pentium processor with mmx technology. it has all the advanced features of the desktop version of the pentium processor with mmx technology except for the differences listed in section 3.1. the mobile pentium processor with mmx technology has several features which allow high- performance notebooks to be designed, including the following: tcp dimensions are ideal for small form-factor designs. tcp has superior thermal resistance characteristics. 2.45v core and 3.3v i/o buffer v cc inputs reduce power consumption significantly, while maintaining 3.3v compatibility externally. the sl enhanced feature set the architecture and internal features of the mobile pentium processor with mmx technology are identical to the desktop version specifications provided in the pentium ? processor family developer?s manual (order number 241428 ) , except several features not used in mobile applications which have been eliminated to streamline it for mobile applications. this document should be used in conjunction with pentium ? processor family developer?s manual (order number: 241428) 2. 0. microprocessor architecture overview the mobile pentium processor with mmx technology extends the mobile pentium family of microprocessors. it is binary compatible with the 8086/88, 80286, intel386? dx, intel386 sx, intel486? dx, intel486 sx, intel486 dx2 and mobile pentium processors with voltage reduction technology (75-150). the mobile pentium processor family consists of the mobile pentium processor with mmx technology described in this document and the mobile pentium processor with voltage reduction technology (75-150). the mobile pentium processor with mmx technology contains all of the features of previous intel architecture and provides significant en- hancements and additions including the following: support for mmx? technology superscalar architecture enhanced branch prediction algorithm pipelined floating-point unit improved instruction execution time separate 16k code and 16k data caches writeback mesi protocol in the data cache 64-bit data bus enhanced bus cycle pipelining address parity internal parity checking execution tracing performance monitoring ieee 1149.1 boundary scan system management mode virtual mode extensions voltage reduction technology sl power management features pool of four write buffers used by both pipes mobile pentium ? processor with mmx? technology 5 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) 2.1. mobile pentium ? processor family architecture the application instruction set of the mobile pentium processor family includes the complete intel486 cpu family instruction set with extensions to accommodate some of the additional functionality of the pentium processors. all application software written for the intel386 and intel486 family microprocessors will run on the pentium processors without modification. the on- chip memory management unit (mmu) is completely compatible with the intel386 and intel486 families of processors. the pentium processors implement several enhancements to increase performance. the two instruction pipelines and floating-point unit on pentium processors are capable of independent operation. each pipeline issues frequently used instructions in a single clock. together, the dual pipes can issue two integer instructions in one clock, or one floating-point instruction (under certain circumstances, two floating-point instructions) in one clock. branch prediction is implemented in the pentium processors. to support this, pentium processors implement two prefetch buffers, one to prefetch code in a linear fashion, and one that prefetches code according to the branch target buffer (btb) so the needed code is almost always prefetched before it is needed for execution. the floating-point unit has been completely redesigned over the intel486 processor. faster algorithms provide up to 10x speed-up for common operations including add, multiply and load. pentium processors include separate code and data caches integrated on-chip to meet performance goals. each cache has a 32-byte line size and is 2-way set associative. each cache has a dedicated translation lookaside buffer (tlb) to translate linear addresses to physical addresses. the data cache is configurable to be writeback or writethrough on a line-by-line basis and follows the mesi protocol. the data cache tags are triple ported to support two data transfers and an inquire cycle in the same clock. the code cache is an inherently write-protected cache. the code cache tags are also triple ported to support snooping and split line accesses. individual pages can be configured as cacheable or non-cacheable by software or hardware. the caches can be enabled or disabled by software or hardware. the pentium processors have increased the data bus to 64 bits to improve the data transfer rate. burst read and burst writeback cycles are supported by the pentium processors. in addition, bus cycle pipelining has been added to allow two bus cycles to be in progress simultaneously. the pentium processors' mmu contains optional extensions to the architecture which allow 4-kbyte and 4-mbyte page sizes. the pentium processors have added significant data integrity and error detection capability. data parity checking is still supported on a byte-by-byte basis. address parity checking and internal parity checking features have been added along with a new exception, the machine check exception. as more and more functions are integrated on chip, the complexity of board level testing is increased. to address this, the pentium processors have increased test and debug capability. the pentium processors implement ieee boundary scan (standard 1149.1). in addition, the pentium processors have specified four breakpoint pins that correspond to each of the debug registers and externally indicate a breakpoint match. execution tracing provides external indications when an instruction has completed execution in either of the two internal pipelines, or when a branch has been taken. system management mode (smm) has been implemented along with some extensions to the smm architecture. enhancements to the virtual 8086 mode have been made to increase performance by reducing the number of times it is necessary to trap to a vir tual 8086 monitor. figure 1 shows a block diagram of the mobile pentium processor with mmx technology. the block diagram shows the two instruction pipelines, the "u" pipe and "v" pipe. the u-pipe can execute all integer and floating-point instructions. the v-pipe can exe cute simple integer instructions and the fxch floating-point instructions. mobile pentium ? processor with mmx? technology 6 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) the separate code and data caches are shown,. the data cache has two ports, one for each of the two pipes (the tags are triple ported to allow simultaneous inquire cycles). the data cache has a dedicated translation lookaside buffer (tlb) to translate linear addresses to the physical addresses used by the data cache. branch target buffer code cache 16 kbytes rom control unit generate address generate data cache 16 kbytes 128 tlb tlb prefetch address prefetch buffers instruction decode instruction pointer integer register file alu barrel shifter 32 32 32 32 32 32 page unit bus unit 32-bit address bus control 64-bit data bus 32-bit addr. bus 64 control register file add multiply divide floating point unit control 80 80 address (u pipeline) (v pipeline) (u pipeline) (v pipeline) alu pp0115 branch verif. & target addr 32 64-bit data bus mmx tm unit v-pipeline connection u-pipeline connection figure 1 . mobile pentium ? processor with mmx? technology block diagram mobile pentium ? processor with mmx? technology 7 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) the code cache, branch target buffer and prefetch buffers are responsible for getting raw instructions into the execution units of the mobile pentium processor. instructions are fetched from the code cache or from the external bus. branch addresses are remembered by the branch target buffer. the code cache tlb translates linear addresses to physical addresses used by the code cache. the decode unit decodes the prefetched instructions so the mobile pentium processor can execute the instruction. the control rom contains the microcode which controls the sequence of operations that must be performed to implement the mobile pentium processor architecture. the control rom unit has direct control over both pipelines. the mobile pentium processor contains a pipelined floating-point unit that provides a significant floating-point performance advantage over previous generations of processors. in addition to the smm features described above, the mobile pentium processor supports clock control. when the clock to the processor is stopped, power dissipation is virtually eliminated. the combination of these improvements makes the mobile pentium processor a good choice for energy-efficient notebook designs. the mobile pentium processor supports fractional bus operation. this allows the internal processor core to operate at high frequencies, while communicating with the external bus at lower frequencies. the architectural features introduced in this section are more fully described in the pentium ? processor family developer's manual (order number: 241428). 2.2. mobile pentium ? processor with mmx tm technology the mobile pentium processor with mmx technology is a significant addition to the mobile pentium processor family. available at both 150 and 166 mhz, it is the first microprocessor to support intel mmx technology and now at 133 mhz. the mobile pentium processor with mmx technology is both software and pin compatible with previous members of the mobile pentium processor family. it contains 4.5 million transistors and is manufactured on lntel's enhanced 0.35 micron cmos process which allows voltage reduction technology for low power and high density. this enables the mobile pentium processor with mmx technology to remain within the thermal envelope while providing a significant performance increase. in addition to the architecture described in the previous section for the mobile pentium processor family, the mobile pentium processor with mmx technology has several additional micro- architectural enhancements, which are described below: 2.3.1. full support for intel mmx tm technology mmx technology is based on simd technique (single instruction, multiple data) which enables increased performance on a wide variety of multimedia and communications applications. fifty- seven new instructions and four new 64-bit data types are supported in the mobile pentium processor with mmx technology. all existing operating system and application software are fully- compatible. 2.3.2. doubled code and data caches to 16k each on-chip level-1 data and code cache sizes have been doubled to 16kb each and are 4-way set associative on the mobile pentium processor with mmx technology. larger separate internal caches improve performance by reducing average memory access time and providing fast access to recently- used instructions and data. the instruction and data caches can be accessed simultaneously while the data cache supports two data references simultaneously. the data cache supports a write- back (or alternatively, write-through, on a line by line basis) policy for memory updates. 2.3.3. improved branch prediction dynamic branch prediction uses the branch target buffer (btb) to boost performance by predicting the most likely set of instructions to be executed. the btb has been improved on the mobile pentium processor with mmx technology to increase its accuracy. further, this processor has four prefetch buffers that can hold up to four successive code streams. mobile pentium ? processor with mmx? technology 8 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) 2.3.4. enhanced pipeline an additional pipeline stage has been added and the pipeline has been enhanced to improve performance. the integration of the mmx technology pipeline with the integer pipeline is very similar to that of the floating-point pipeline. under some circumstances, two mmx instructions or one integer and one mmx instruction can be paired and issued in one clock cycle to increase throughput. the enhanced pipeline is described in more detail in the pentium ? processor family developer?s manual (order number 241428). deeper write buffers. a pool of four write buffers is now shared between the dual pipelines to improve memory write performance. 3.0. mobile pentium ? processor with mmx? technology pinout 3.1. mobile differences from desktop to better streamline the part for mobile applications, the following features have been eliminated: upgrade, dual processing (dp), apic and master/checker functional redundancy. table 1 lists the corresponding pins which exist on the desktop pentium processor with mmx technology but have been removed on the mobile pentium processor with mmx technology. table 1 . signals removed in mobile pentium ? processor with mmx? technology signal function adsc# additional address status. this signal is mainly used for large or standalone l2 cache memory subsystem support required for high-performance desktop or server models. brdyc# additional burst ready. this signal is mainly used for large or standalone l2 cache memory subsystem support required for high-performance desktop or server models. cputyp cpu type. this signal is used for dual processing systems. d/p# dual/primary processor identification. this signal is only used for an upgrade processor. frcmc# functional redundancy checking. this signal is only used for error detection via processor redundancy and requires two pentium ? processors (master/checker). pbgnt# private bus grant. this signal is only used for dual processing systems. pbreq# private bus request. this signal is used only for dual processing systems. phit# private hit. this signal is only used for dual processing systems. phitm# private modified hit. this signal is only used for dual processing systems. picclk apic clock. this signal is the apic interrupt controller serial data bus clock. picd0 [dpen#] apic?s programmable interrupt controller data line 0. picd0 shares a pin with dpen# (dual processing enable). picd1 [apicen] apic?s programmable interrupt controller data line 1. picd1 shares a pin with apicen (apic enable (on reset)). mobile pentium ? processor with mmx? technology 9 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) 3.2. tcp pinout and pin descriptions the text orientation on the top side view drawings in this section represent the orientation of the ink mark on the actual packages (note that the text shown in this section is not the actual text which will be marked on the packages). 3.2.1. tcp mobile pentium ? processor with mmx? technology pinout v c c 2 2 4 0 2 3 9 2 3 8 2 3 7 2 3 6 2 3 5 2 3 4 2 3 3 2 3 2 2 3 1 2 3 0 v s s a 1 1 a 1 0 v c c 3 v s s a 9 v s s v c c 2 a 8 v c c 3 2 1 9 2 1 8 2 1 7 2 1 6 2 1 5 2 1 4 2 1 3 2 1 2 2 1 1 2 1 0 a 3 v s s v c c 2 v c c 3 v s s a 3 1 a 3 0 a 2 9 a 2 8 v c c 3 2 2 9 2 2 8 2 2 7 2 2 6 2 2 5 2 2 4 2 2 3 2 2 2 2 2 1 2 2 0 v s s a 7 a 6 v c c 3 v c c 2 v s s a 5 a 4 v c c 3 v s s 2 0 9 2 0 8 2 0 7 2 0 6 2 0 5 2 0 4 2 0 3 2 0 2 2 0 1 2 0 0 v s s a 2 7 a 2 6 a 2 5 a 2 4 v c c 3 v s s a 2 3 a 2 2 a 2 1 1 9 9 1 9 8 1 9 7 1 9 6 1 9 5 1 9 4 1 9 3 1 9 2 1 9 1 1 9 0 n m i r / s # i n t r s m i # v c c 2 v s s i g n n e # i n i t p e n # v c c 2 1 8 9 1 8 8 1 8 7 1 8 6 1 8 5 1 8 4 1 8 3 1 8 2 1 8 1 1 8 0 v s s v c c 2 v s s b f 0 b f 1 n c v c c 2 v s s s t p c l k # v c c 2 1 7 9 1 7 8 1 7 7 1 7 6 1 7 5 1 7 4 1 7 3 1 7 2 1 7 1 1 7 0 v s s v c c 3 v c c 2 v s s n c v c c 2 v s s v c c 2 v s s v c c 2 1 6 9 1 6 8 1 6 7 1 6 6 1 6 5 1 6 4 1 6 3 1 6 2 1 6 1 v s s v c c 2 t r s t # v s s v c c 2 t m s t d i t d o t c k v c c 2 1 2 3 4 5 6 7 8 9 1 0 1 1 v c c 3 v s s h o l d w b / w t # v c c 2 n a # b o f f # b r d y # v c c 2 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 m / i o # v c c 3 v s s b p 3 v s s v c c 2 b p 2 p m 1 / b p 1 p m 0 / b p 0 f e r r # 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 v s s k e n # a h o l d i n v e w b e # v c c 2 v s s v c c 3 v s s c a c h e # 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 v s s v c c 2 i e r r # v c c 3 v s s d p 7 d 6 3 d 6 2 d 6 1 v c c 2 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 v s s v c c 3 v s s d 6 0 d 5 9 d 5 8 d 5 7 v c c 2 v s s v c c 3 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 v s s d 5 6 d p 6 d 5 5 d 5 4 v c c 2 v s s v c c 3 v s s d 5 3 6 2 6 3 6 4 6 5 6 6 6 7 6 8 6 9 7 0 7 1 d 5 2 d 5 1 d 5 0 v c c 2 v s s v c c 3 v s s d 4 9 d 4 8 d p 5 7 2 7 3 7 4 7 5 7 6 7 7 7 8 7 9 8 0 d 4 7 v c c 3 v s s d 4 6 d 4 5 d 4 4 d 4 3 v c c 3 v s s v s s pp0116 figure 2 . tcp mobile pentium ? processor with mmx? technology pinout mobile pentium ? processor with mmx? technology 10 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) 3.2.2. tcp mobile pentium ? processor with mmx? technology pin cross reference table 2 . tcp pin cross reference by pin name address a3 219 a9 234 a15 251 a21 200 a27 208 a4 222 a10 237 a16 254 a22 201 a28 211 a5 223 a11 238 a17 255 a23 202 a29 212 a6 227 a12 242 a18 259 a24 205 a30 213 a7 228 a13 245 a19 262 a25 206 a31 214 a8 231 a14 248 a20 265 a26 207 data d0 152 d13 132 d26 107 d39 87 d52 62 d1 151 d14 131 d27 106 d40 83 d53 61 d2 150 d15 128 d28 105 d41 82 d54 56 d3 149 d16 126 d29 102 d42 81 d55 55 d4 146 d17 125 d30 101 d43 78 d56 53 d5 145 d18 122 d31 100 d44 77 d57 48 d6 144 d19 121 d32 96 d45 76 d58 47 d7 143 d20 120 d33 95 d46 75 d59 46 d8 139 d21 119 d34 94 d47 72 d60 45 d9 138 d22 116 d35 93 d48 70 d61 40 d10 137 d23 115 d36 90 d49 69 d62 39 d11 134 d24 113 d37 89 d50 64 d63 38 d12 133 d25 108 d38 88 d51 63 mobile pentium ? processor with mmx? technology 11 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) table 2. tcp pin cross reference by pin name (contd.) control a20m# 286 breq 312 hitm# 293 pm0/bp0 30 ads# 296 buschk# 288 hlda 311 pm1/bp1 29 ahold 14 cache# 21 hold 4 prdy 318 ap 308 d/c# 298 ierr# 34 pwt 299 apchk# 315 dp0 140 ignne# 193 r/s# 198 be0# 285 dp1 127 init 192 reset 270 be1# 284 dp2 114 intr/lint0 197 scyc 273 be2# 283 dp3 99 inv 15 smi# 196 be3# 282 dp4 84 ken# 13 smiact# 319 be4# 279 dp5 71 lock# 303 tck 161 be5# 278 dp6 54 m/io# 22 tdi 163 be6# 277 dp7 37 na# 8 tdo 162 be7# 276 eads# 297 nmi/lint1 199 tms 164 boff# 9 ewbe# 16 pcd 300 trst# 167 bp2 28 ferr# 31 pchk# 316 w/r# 289 bp3 25 flush# 287 pen# 191 wb/wt# 5 brdy# 10 hit# 292 clock control bf 0 186 bf1 185 clk 272 stpclk# 181 mobile pentium ? processor with mmx? technology 12 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) table 2. tcp pin cross reference by pin name (contd.) v cc2 1 1 111 183 257 6 153 188 260 11 157 190 266 17 165 195 268 27 168 217 304 33 170 225 309 41 172 232 317 49 174 240 57 177 243 65 180 249 v cc3 2 2 91 178 258 19 97 204 264 23 103 210 275 35 109 216 281 43 117 221 291 51 123 226 295 59 129 230 301 67 135 236 306 73 141 241 313 79 147 247 85 160 253 mobile pentium ? processor with mmx? technology 13 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) table 2. tcp pin cross reference by pin name (contd.) v ss 3 80 173 246 7 86 176 250 12 92 179 252 18 98 182 256 20 104 187 261 24 110 189 263 26 112 194 267 32 118 203 269 36 124 209 274 42 130 215 280 44 136 218 290 50 142 220 294 52 148 224 302 58 154 229 305 60 159 233 307 66 166 235 310 68 169 239 314 74 171 244 320 nc 155 158 184 156 175 271 note: 1. these v cc2 pins are 2.45v inputs to the core, but may change to a different voltage on future offerings of this microprocessor family. 2. all v cc3 pins are 3.3v i/o power inputs. mobile pentium ? processor with mmx? technology 14 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) table 3 . tcp pin cross references by pin number (pins 1-160) pin # signal pin # signal pin # signal pin # signal 1 v cc2 41 v cc2 81 d42 121 d19 2 v cc3 42 v ss 82 d41 122 d18 3 v ss 43 v cc3 83 d40 123 v cc3 4 hold 44 v ss 84 dp4 124 v ss 5 wb/wt# 45 d60 85 v cc3 125 d17 6 v cc2 46 d59 86 v ss 126 d16 7 v ss 47 d58 87 d39 127 dp1 8 na# 48 d57 88 d38 128 d15 9 boff# 49 v cc2 89 d37 129 v cc3 10 brdy# 50 v ss 90 d36 130 v ss 11 v cc2 51 v cc3 91 v cc3 131 d14 12 v ss 52 v ss 92 v ss 132 d13 13 ken# 53 d56 93 d35 133 d12 14 ahold 54 dp6 94 d34 134 d11 15 inv 55 d55 95 d33 135 v cc3 16 ewbe# 56 d54 96 d32 136 v ss 17 v cc2 57 v cc2 97 v cc3 137 d10 18 v ss 58 v ss 98 v ss 138 d9 19 v cc3 59 v cc3 99 dp3 139 d8 20 v ss 60 v ss 100 d31 140 dp0 21 cache# 61 d53 101 d30 141 v cc3 22 m/io# 62 d52 102 d29 142 v ss 23 v cc3 63 d51 103 v cc3 143 d7 24 v ss 64 d50 104 v ss 144 d6 25 bp3 65 v cc2 105 d28 145 d5 26 vss 66 v ss 106 d27 146 d4 27 v cc2 67 v cc3 107 d26 147 v cc3 28 bp2 68 v ss 108 d25 148 v ss 29 pm1/bp1 69 d49 109 v cc3 149 d3 mobile pentium ? processor with mmx? technology 15 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) table 3 . tcp pin cross references by pin number (pins 1-160) pin # signal pin # signal pin # signal pin # signal 30 pm0/bp0 70 d48 110 vss 150 d2 31 ferr# 71 dp5 111 v cc2 151 d1 32 v ss 72 d47 112 v ss 152 d0 33 v cc2 73 v cc3 113 d24 153 v cc2 34 ierr# 74 v ss 114 dp2 154 v ss 35 v cc3 75 d46 115 d23 155 nc 36 v ss 76 d45 116 d22 156 nc 37 dp7 77 d44 117 v cc3 157 v cc2 38 d63 78 d43 118 v ss 158 nc 39 d62 79 v cc3 119 d21 159 v ss 40 d61 80 v ss 120 d20 160 v cc3 161 tck 201 a22 241 v cc3 281 v cc3 162 tdo 202 a23 242 a12 282 be3# 163 tdi 203 v ss 243 v cc2 283 be2# 164 tms 204 v cc3 244 v ss 284 be1# 165 v cc2 205 a24 245 a13 285 be0# 166 v ss 206 a25 246 v ss 286 a20m# 167 trst# 207 a26 247 v cc3 287 flush# 168 v cc2 208 a27 248 a14 288 buschk# 169 v ss 209 v ss 249 v cc2 289 w/r# 170 v cc2 210 v cc3 250 v ss 290 v ss 171 v ss 211 a28 251 a15 291 v cc3 172 v cc2 212 a29 252 v ss 292 hit# 173 v ss 213 a30 253 v cc3 293 hitm# 174 v cc2 214 a31 254 a16 294 v ss 175 nc 215 v ss 255 a17 295 v cc3 176 v ss 216 v cc3 256 v ss 296 ads# 177 v cc2 217 v cc2 257 v cc2 297 eads# 178 v cc3 218 v ss 258 v cc3 298 d/c# 179 v ss 219 a3 259 a18 299 pwt mobile pentium ? processor with mmx? technology 16 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) table 3 . tcp pin cross references by pin number (pins 1-160) pin # signal pin # signal pin # signal pin # signal 180 v cc2 220 v ss 260 v cc2 300 pcd 181 stpclk# 221 v cc3 261 v ss 301 v cc3 182 v ss 222 a4 262 a19 302 v ss 183 v cc2 223 a5 263 v ss 303 lock# 184 nc 224 v ss 264 v cc3 304 v cc2 185 bf1 225 v cc2 265 a20 305 v ss 186 bf 0 226 v cc3 266 v cc2 306 v cc3 187 v ss 227 a6 267 v ss 307 v ss 188 v cc2 228 a7 268 v cc2 308 ap 189 v ss 229 v ss 269 v ss 309 v cc2 190 v cc2 230 v cc3 270 reset 310 v ss 191 pen# 231 a8 271 nc 311 hlda 192 init 232 v cc2 272 clk 312 breq 193 ignne# 233 v ss 273 scyc 313 v cc3 194 v ss 234 a9 274 v ss 314 v ss 195 v cc2 235 v ss 275 v cc3 315 apchk# 196 smi# 236 v cc3 276 be7# 316 pchk# 197 intr/lint0 237 a10 277 be6# 317 v cc2 198 r/s# 238 a11 278 be5# 318 prdy 199 nmi/lint1 239 v ss 279 be4# 319 smiact# 200 a21 240 v cc2 280 v ss 320 v ss note: 1. v cc2 pins are 2.45v inputs to the core. 2. v cc3 pins are 3.3v inputs to the i/o. mobile pentium ? processor with mmx? technology 17 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) 3.3. ppga package the text orientation on the top side view drawings in this section represent the orientation of the ink mark on the actual packages (note that the text shown in this section is not the actual text which will be marked on the packages). 3.3.1. ppga pin diagrams 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 i n c i n c i n c f l u s h # v c c 2 v c c 3 a 1 0 a 6 n c e a d s # w / r # v s s v s s v s s v s s v s s v s s v s s v s s v s s v s s v s s v s s a 8 a 4 a 3 0 v c c 2 d e t # p w t h i t m # b u s c h k # b e 0 # b e 2 # b e 4 # b e 6 # s c y c a 2 0 a 1 8 a 1 6 a 1 4 a 1 2 a 1 1 a 7 a 3 a p d / c # h i t # a 2 0 m # b e 1 # b e 3 # b e 5 # b e 7 # c l k r e s e t a 1 9 a 1 7 a 1 5 a 1 3 a 9 a 5 a 2 9 a 2 8 a 2 5 a 3 1 a 2 6 a 2 2 v c c 3 a 2 4 a 2 7 a 2 1 v s s a 2 3 i n t r v s s r / s # n m i s m i # v s s i n i t i g n n e # p e n # v s s v s s s t p c l k # v s s v s s n c v s s t r s t # t m s v s s t d o t d i t c k v s s d 0 v s s d 2 v s s d 3 d 1 d 5 d 4 d 7 d 6 d p 0 d 8 d 1 2 d p 1 d 9 d 1 0 d 1 4 d 1 7 d 2 1 d 1 1 d 1 3 d 1 6 d 2 0 n c d 1 5 d 1 8 d 2 2 v c c 3 b r e q h l d a a d s # v s s l o c k # v c c 2 s m i a c t # p c d v s s p c h k # a p c h k # v s s p r d y v s s h o l d w b / w t # v s s b o f f # n a # v s s b r d y # e w b e # k e n # v s s a h o l d c a c h e # i n v v s s m i / o # b p 2 b p 3 v s s p m 1 b p 1 p m 0 b p 0 f e r r # v s s i e r r # d 6 3 d p 7 v s s d 6 2 d 6 1 d 6 0 v s s d 5 9 d 5 7 d 5 8 v s s d 5 6 d 5 5 d 5 3 d p 6 d 5 1 d p 5 d 5 4 d 5 2 d 4 9 d 4 6 d 4 2 d 5 0 d 4 8 d 4 4 d 4 0 d 3 9 i n c d 4 7 d 4 5 d p 4 d 3 8 d 3 6 i n c d 4 3 v s s v s s v s s v s s v s s v s s v s s v s s v s s v s s v s s v s s d 3 7 d 3 5 d 3 3 d p 3 d 3 0 d 3 4 d 3 2 d 3 1 d 2 9 d 2 7 i n c d 4 1 v c c 2 d 2 8 d 2 5 d 2 6 d p 2 d 2 3 d 2 4 d 1 9 v c c 3 v c c 3 n c n c v c c 3 v s s n c n c b f 1 b f 0 v s s v s s v s s n c a n a m a l a k a j a h a g a f a e a d a c a b a a z y x w v u t s r q p n m l k j h g f e d c b a a n a m a l a k a j a h a g a f a e a d a c a b a a z y x w v u t s r q p n m l k j h g f e d c b a p p 0 1 1 4 v c c 3 v c c 3 v c c 3 v c c 3 v c c 2 v c c 2 v c c 2 v c c 2 v c c 2 v c c 2 v c c 2 v c c 2 v c c 2 v c c 2 v c c 2 v c c 2 v c c 2 v c c 2 v c c 2 v c c 2 v c c 2 v c c 2 v c c 2 v c c 2 v c c 2 v c c 2 v c c 3 v c c 3 v c c 3 v c c 3 v c c 3 v c c 3 v c c 3 v c c 3 v c c 3 v c c 3 v c c 3 v c c 3 v c c 3 v c c 3 v c c 3 v c c 3 v c c 3 v c c 3 n c n c n c n c n c n c n c n c n c n c n c n c note all inc and nc pins must remain unconnected. connection of nc pins may result in component failure or incompatibility with processor steppings. figure 3 . mobile pentium ? processor with mmx? technology pinout top side view mobile pentium ? processor with mmx? technology 18 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) inc inc inc flush# vcc2 vcc3 a10 a6 nc eads# w/r# vss vss vss vss vss vss vss vss vss vss vss vss a8 a4 a30 pwt hitm# buschk# be0# be2# be4# be6# scyc a20 a18 a16 a14 a12 a11 a7 a3 ap d/c# hit# a20m# be1# be3# be5# be7# clk reset a19 a17 a15 a13 a9 a5 a29 a28 a25 a31 a26 a22 vcc3 a24 a27 a21 vss a23 intr vss r/s# nmi smi# vss init ignne# pen# vss vss stpclk# vss vss nc vss trst# tms vss tdo tdi tck vss d0 vss d2 vss d3 d1 d5 d4 d7 d6 dp0 d8 d12 dp1 d9 d10 d14 d17 d21 d11 d13 d16 d20 nc d15 d18 d22 vcc3 breq hlda ads# vss lock# vcc2 smiact# pcd vss pchk# apchk# vss prdy vss hold wb/wt# vss boff# na# vss brdy# ewbe# ken# vss ahold cache# inv vss mi/o# bp2 bp3 vss pm1bp1 pm0bp0 ferr# vss ierr# d63 dp7 vss d62 d61 d60 vss d59 d57 d58 vss d56 d55 d53 dp6 d51 dp5 d54 d52 d49 d46 d42 d50 d48 d44 d40 d39 inc d47 d45 dp4 d38 d36 inc d43 vss vss vss vss vss vss vss vss vss vss vss vss d37 d35 d33 dp3 d30 d34 d32 d31 d29 d27 inc d41 vcc2 d28 d25 d26 dp2 d23 d24 d19 vcc3 vcc3 nc nc vcc3 vss nc nc bf1 bf0 vss vss vss nc an am al ak aj ah ag af ae ad ac ab aa z y x w v u t s r q p n m l k j h g f e d c b a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 an am al ak aj ah ag af ae ad ac ab aa z y x w v u t s r q p n m l k j h g f e d c b a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 pp0113 v cc 2 det# pentium? processor with mmx? technology pin side view vcc2 vcc2 vcc2 vcc2 vcc2 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 nc nc nc nc nc nc nc nc nc nc nc nc note all inc and nc pins must remain unconnected. connection of nc pins may result in component failure or incompatibility with processor steppings. figure 4 . mobile pentium? processor with mmx? technology pinout pin side view mobile pentium ? processor with mmx? technology 19 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) 3.3.2 ppga mob ile pentium? processor with mmx? technology pin cross reference table 4 . ppga pin cross reference by pin name address a3 al35 a9 ak30 a15 ak26 a21 af34 a27 ag33 a4 am34 a10 an31 a16 al25 a22 ah36 a28 ak36 a5 ak32 a11 al31 a17 ak24 a23 ae33 a29 ak34 a6 an33 a12 al29 a18 al23 a24 ag35 a30 am36 a7 al33 a13 ak28 a19 ak22 a25 aj35 a31 aj33 a8 am32 a14 al27 a20 al21 a26 ah34 data d0 k34 d13 b34 d26 d24 d39 d10 d52 e03 d1 g35 d14 c33 d27 c21 d40 d08 d53 g05 d2 j35 d15 a35 d28 d22 d41 a05 d54 e01 d3 g33 d16 b32 d29 c19 d42 e09 d55 g03 d4 f36 d17 c31 d30 d20 d43 b04 d56 h04 d5 f34 d18 a33 d31 c17 d44 d06 d57 j03 d6 e35 d19 d28 d32 c15 d45 c05 d58 j05 d7 e33 d20 b30 d33 d16 d46 e07 d59 k04 d8 d34 d21 c29 d34 c13 d47 c03 d60 l05 d9 c37 d22 a31 d35 d14 d48 d04 d61 l03 d10 c35 d23 d26 d36 c11 d49 e05 d62 m04 d11 b36 d24 c27 d37 d12 d50 d02 d63 n03 d12 d32 d25 c23 d38 c09 d51 f04 mobile pentium ? processor with mmx? technology 20 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) table 4. ppga pin cross reference by pin name (contd.) control a20m# ak08 breq aj01 hitm# al05 pm1/bp1 r04 ads# aj05 buschk# al07 hlda aj03 r/s# ac35 ahold v04 cache# u03 hold ab04 prdy ac05 ap ak02 d/c# ak04 ierr# p04 pwt al03 apchk# ae05 dp0 d36 ignne# aa35 reset ak20 be0# al09 dp1 d30 init aa33 scyc al17 be1# ak10 dp2 c25 intr ad34 smi# ab34 be2# al11 dp3 d18 inv u05 smiact# ag03 be3# ak12 dp4 c07 ken# w05 tck m34 be4# al13 dp5 f06 lock# ah04 tdi n35 be5# ak14 dp6 f02 m/io# t04 tdo n33 be6# al15 dp7 n05 na# y05 tms p34 be7# ak16 eads# am04 nmi ac33 trst# q33 boff# z04 ewbe# w03 pcd ag05 vcc2det# al01 bp2 s03 ferr# q05 pchk# af04 w/r# am06 bp3 s05 flush# an07 pen# z34 wb/wt# aa05 brdy# x04 hit# ak06 pm0/bp0 q03 clock control clk ak18 bf0 y33 bf1 x34 stpclk# v34 mobile pentium ? processor with mmx? technology 21 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) table 4. ppga pin cross reference by pin name (contd.) v cc2 1 a17 a07 q01 aa01 an11 a15 g01 s01 ac01 an13 a13 j01 u01 ae01 an15 a11 l01 w01 ag01 an17 a09 n01 y01 an09 an19 v cc3 2 a19 a27 j37 q37 u37 ac37 an27 a21 a29 l37 s37 w37 ae37 an25 a23 e37 l33 t34 y37 ag37 an23 a25 g37 n37 u33 aa37 an29 an21 v ss b06 b18 h02 p02 u35 z36 af36 am12 am24 b08 b20 h36 p36 v02 ab02 ah02 am14 am26 b10 b22 k02 r02 v36 ab36 aj37 am16 am28 b12 b24 k36 r36 x02 ad02 al37 am18 am30 b14 b26 m02 t02 x36 ad36 am08 am20 an37 b16 b28 m36 t36 z02 af02 am10 am22 nc a37 s35 ad04 h34 y03 ae03 j33 y35 ae35 l35 w33 al01 q35 w35 al19 r34 aa03 am02 s33 ac03 an35 inc a03 b02 c01 an01 an03 an05 note: 1. these v cc2 pins are 2.45v inputs to the core, but may change to a different voltage on future offerings of this microprocessor family. 2. all v cc3 pins are 3.3v power inputs to the i/o. mobile pentium ? processor with mmx? technology 22 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) 3.4. design notes for reliable operation, always connect unused inputs to an appropriate signal level. unused active low inputs should be connected to v cc3 . unused active high inputs should be connected to gnd (v ss ). no connect (nc) pins must remain unconnected. connection of nc and inc pins may result in component failure or incompatibility with processor steppings. 3.5. quick pin reference this section gives a brief functional description of each of the pins. for a detailed description, see the hardware interface chapter in the pentium ? processor family developer's manual. note all input pins must meet their ac/dc specifications to guarantee proper functional behavior. the # symbol at the end of a signal name indicates that the active or asserted state occurs when the signal is at a low voltage. when a # symbol is not present after the signal name, the signal is active, or asserted at the high voltage level. square brackets around a signal name indicate that the signal is defined only at reset. the pins are classified as input or output based on their function in master mode. see the error detection chapter of the pentium ? processor family developer?s manual, for further information. mobile pentium ? processor with mmx? technology 23 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) table 5 . quick pin reference symbol type name and function a20m# i when the address bit 20 mask pin is asserted, the mobile pentium ? processor with mmx? technology emulates the address wraparound at 1 mbyte which occurs on the 8086. when a20m# is asserted, the processor masks physical address bit 20 (a20) before performing a lookup to the internal caches or driving a memory cycle on the bus. the effect of a20m# is undefined in protected mode. a20m# must be asserted only when the processor is in real mode. a31-a3 i/o as outputs, the address lines of the processor along with the byte enables define the physical area of memory or i/o accessed. the external system drives the inquire address to the processor on a31-a5. ads# o the address status indicates that a new valid bus cycle is currently being driven by the processor. ahold i in response to the assertion of address hold , the processor will stop driving the address lines (a31-a3), and ap in the next clock. the rest of the bus will remain active so data can be returned or driven for previously issued bus cycles. ap i/o address parity is driven by the processor with even parity information on all processor generated cycles in the same clock that the address is driven. even parity must be driven back to the processor during inquire cycles on this pin in the same clock as eads# to ensure that correct parity check status is indicated. apchk# o the address parity check status pin is asserted two clocks after eads# is sampled active if the processor has detected a parity error on the address bus during inquire cycles. apchk# will remain active for one clock each time a parity error is detected. be7#-be5# be4#-be0# o i/o the byte enable pins are used to determine which bytes must be written to external memory, or which bytes were requested by the cpu for the current cycle. the byte enables are driven in the same clock as the address lines (a31 -3). bf[0:1] i the bus frequency pins determine the bus-to-core frequency ratio. bf [1:0] are sampled at reset, and cannot be changed until another non-warm (1 ms) assertion of reset. additionally, bf[1:0] must not change values while reset is active. see table 6 for bus frequency selection. in order to override the internal defaults and guarantee that the bf[0:1] inputs remain stable while reset is active, these pins should be strapped directly to or through a pullup/pulldown resistor to vcc3 or ground. drving these pins with active logic is not recommended unless stability during reset can be guaranteed. during power up, reset should be asserted prior to or ramped simultaneously with the core voltage supply to the processor. boff# i the backoff input is used to abort all outstanding bus cycles that have not yet completed. in response to boff#, the processor will float all pins normally floated during bus hold in the next clock. the processor remains in bus hold until boff# is negated, at which time the processor restarts the aborted bus cycle(s) in their entirety. mobile pentium ? processor with mmx? technology 24 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) table 5. quick pin reference (contd.) symbol type name and function bp[3:2] pm/bp[1:0] o the breakpoint pins (bp3-0) correspond to the debug registers, dr3-dr0. these pins externally indicate a breakpoint match when the debug registers are programmed to test for breakpoint matches. bp1 and bp0 are multiplexed with the performance monitoring pins (pm1 and pm0). the pb1 and pb0 bits in the debug mode control register determine if the pins are configured as breakpoint or performance monitoring pins. the pins come out of reset configured for performance monitoring. brdy# i the burst ready input indicates that the external system has presented valid data on the data pins in response to a read or that the external system has accepted the processor data in response to a write request. this signal is sampled in the t2, t12 and t2p bus states. breq o the bus request output indicates to the external system that the processor has internally generated a bus request. this signal is always driven whether or not the processor is driving its bus. buschk# i the bus check input allows the system to signal an unsuccessful completion of a bus cycle. if this pin is sampled active, the processor will latch the address and control signals in the machine check registers. if, in addition, the mce bit in cr4 is set, the processor will vector to the machine check exception. note: to assure that buschk# will always be recognized, stpclk# must be deasserted any time buschk# is asserted by the system, before the system allows another external bus cycle. if buschk# is asserted by the system for a snoop cycle while stpclk# remains asserted, usually (if mce=1) the processor will vector to the exception after stpclk# is deasserted. but if another snoop to the same line occurs during stpclk# assertion, the processor can lose the buschk# request. cache# o for processor-initiated cycles, the cache pin indicates internal cacheability of the cycle (if a read), and indicates a burst writeback cycle (if a write). if this pin is driven inactive during a read cycle, the processor will not cache the returned data, regardless of the state of the ken# pin. this pin is also used to determine the cycle length (number of transfers in the cycle). clk i the clock input provides the fundamental timing for the processor. its frequency is the operating frequency of the processor external bus and requires ttl levels. all external timing parameters except tdi, tdo, tms, trst# and picd0-1 are specified with respect to the rising edge of clk. this pin is 3.3v-tolerant-only on the pentium processor with mmx technology. note: it is recommended that clk begin 150 ms after v cc reaches its proper operating level. this recommendation is only to assure the long term reliability of the device. d/c o the data/code output is one of the primary bus cycle definition pins. it is driven valid in the same clock as the ads# signal is asserted. d/c# distinguishes between data and code or special cycles. mobile pentium ? processor with mmx? technology 25 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) table 5. quick pin reference (contd.) symbol type name and function d63-d0 i/o these are the 64 data lines for the processor. lines d7-d0 define the least significant byte of the data bus; lines d63-d56 define the most significant byte of the data bus. when the cpu is driving the data lines, they are driven during the t2, t12 or t2p clocks for that cycle. during reads, the cpu samples the data bus when brdy# is returned. dp7-dp0 i/o these are the data parity pins for the processor. there is one for each byte of the data bus. they are driven by the processor with even parity information on writes in the same clock as write data. even parity information must be driven back to the pentium processor with voltage reduction technology on these pins in the same clock as the data to ensure that the correct parity check status is indicated by the processor. dp7 applies to d63-d56; dp0 applies to d7-d0. eads# i this signal indicates that a valid external address has been driven onto the processor address pins to be used for an inquire cycle. ewbe# i the external write buffer empty input, when inactive (high), indicates that a write cycle is pending in the external system. when the processor generates a write and ewbe# is sampled inactive, the processor will hold off all subsequent writes to all e- or m-state lines in the data cache until all write cycles have completed, as indicated by ewbe# being active. ferr# o the floating-point error pin is driven active when an unmasked floating-point error occurs. ferr# is similar to the error# pin on the intel387? math coprocessor. ferr# is included for compatibility with systems using ms-dos type floating-point error reporting. flush# i when asserted, the cache flush input forces the processor to write back all modified lines in the data cache and invalidate its internal caches. a flush acknowledge special cycle will be generated by the processor indicating completion of the writeback and invalidation. note: if flush# is sampled low when reset transitions from high to low, tristate test mode is entered. hit# o the hit indication is driven to reflect the outcome of an inquire cycle. if an inquire cycle hits a valid line in either the data or instruction cache, this pin is asserted two clocks after eads# is sampled asserted. if the inquire cycle misses the cache, this pin is negated two clocks after eads#. this pin changes its value only as a result of an inquire cycle and retains its value between the cycles. hitm# o the hit to a modified line output is driven to reflect the outcome of an inquire cycle. it is asserted after inquire cycles which resulted in a hit to a modified line in the data cache. it is used to inhibit another bus master from accessing the data until the line is completely written back. hlda o the bus hold acknowledge pin goes active in response to a hold request driven to the processor on the hold pin. it indicates that the processor has floated most of the output pins and relinquished the bus to another local bus master. when leaving bus hold, hlda will be driven inactive and the processor will resume driving the bus. if the processor has a bus cycle pending, it will be driven in the same clock that hlda is de-asserted. mobile pentium ? processor with mmx? technology 26 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) table 5. quick pin reference (contd.) symbol type name and function hold i in response to the bus hold request , the processor will float most of its output and input/output pins and assert hlda after completing all outstanding bus cycles. the processor will maintain its bus in this state until hold is de-asserted. hold is not recognized during lock cycles. the processor will recognize hold during reset. ierr# o the internal error pin is used to indicate internal parity errors. if a parity error occurs on a read from an internal array, the processor will assert the ierr# pin for one clock and then shutdown. ignne# i this is the ignore numeric error input. this pin has no effect when the ne bit in cr0 is set to 1. when the cr0.ne bit is 0, and the ignne# pin is asserted, the processor will ignore any pending unmasked numeric exception and continue executing floating-point instructions for the entire duration that this pin is asserted. when the cr0.ne bit is 0, ignne# is not asserted, a pending unmasked numeric exception exists (sw.es = 1), and the floating-point instruction is one of finit, fclex, fstenv, fsave, fstsw, fstcw, feni, fdisi, or fsetpm, the processor will execute the instruction in spite of the pending exception. when the cr0.ne bit is 0, ignne# is not asserted, a pending unmasked numeric exception exists (sw.es = 1), and the floating-point instruction is one other than finit, fclex, fstenv, fsave, fstsw, fstcw, feni, fdisi, or fsetpm, the processor will stop execution and wait for an external interrupt. init i the processor initialization input pin forces the processor to begin execution in a known state. the processor state after init is the same as the state after reset except that the internal caches, write buffers, and floating-point registers retain the values they had prior to init. init may not be used in lieu of reset after power up. if init is sampled high when reset transitions from high to low, the processor will perform built-in self test prior to the start of program execution. intr i an active maskable interrupt input indicates that an external interrupt has been generated. if the if bit in the eflags register is set, the processor will generate two locked interrupt acknowledge bus cycles and vector to an interrupt handler after the current instruction execution is completed. intr must remain active until the first interrupt acknowledge cycle is generated to assure that the interrupt is recognized. inv i the invalidation input determines the final cache line state (s or i) in case of an inquire cycle hit. it is sampled together with the address for the inquire cycle in the clock eads# is sampled active. ken# i the cache enable pin is used to determine whether the current cycle is cacheable or not and is consequently used to determine cycle length. when the processor generates a cycle that can be cached (cache# asserted) and ken# is active, the cycle will be transformed into a burst line fill cycle. mobile pentium ? processor with mmx? technology 27 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) table 5. quick pin reference (contd.) symbol type name and function lock# o the bus lock pin indicates that the current bus cycle is locked. the processor will not allow a bus hold when lock# is asserted (but ahold and boff# are allowed). lock# goes active in the first clock of the first locked bus cycle and goes inactive after the brdy# is returned for the last locked bus cycle. lock# is guaranteed to be de-asserted for at least one clock between back-to-back locked cycles. m/io# o the memory/input-output is one of the primary bus cycle definition pins. it is driven valid in the same clock as the ads# signal is asserted. m/io# distinguishes between memory and i/o cycles. na# i an active next address input indicates that the external memory system is ready to accept a new bus cycle although all data transfers for the current cycle have not yet completed. the processor will issue ads# for a pending cycle two clocks after na# is asserted. the processor supports up to two outstanding bus cycles. nmi i the non-maskable interrupt request signal indicates that an external non- maskable interrupt has been generated. pcd o the page cache disable pin reflects the state of the pcd bit in cr3; page directory entry or page table entry. the purpose of pcd is to provide an external cacheability indication on a page-by-page basis. pchk# o the parity check output indicates the result of a parity check on a data read. it is driven with parity status two clocks after brdy# is returned. pchk# remains low one clock for each clock in which a parity error was detected. parity is checked only for the bytes on which valid data is returned. pen# i the parity enable input (along with cr4.mce) determines whether a machine check exception will be taken as a result of a data parity error on a read cycle. if this pin is sampled active in the clock, a data parity error is detected. the processor will latch the address and control signals of the cycle with the parity error in the machine check registers. if, in addition, the machine check enable bit in cr4 is set to "1", the processor will vector to the machine check exception before the beginning of the next instruction. pm/bp[1:0] o these pins function as part of the performance monitoring feature. the breakpoint 1-0 pins are multiplexed with the performance monitoring 1 -0 pins. the pb1 and pb0 bits in the debug mode control register determine if the pins are configured as breakpoint or performance monitoring pins. the pins come out of reset configured for performance monitoring. prdy o the probe ready output pin indicates that the processor has stopped normal execution in response to the r/s# pin going active or probe mode being entered. pwt o the page writethrough pin reflects the state of the pwt bit in cr3, the page directory entry, or the page table entry. the pwt pin is used to provide an external writeback indication on a page-by-page basis. mobile pentium ? processor with mmx? technology 28 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) table 5. quick pin reference (contd.) symbol type name and function r/s# i the run/stop input is provided for use with the intel debug port. please refer to the pentium ? processor family developer?s manual (order number 241428) for more details. reset i reset forces the processor to begin execution at a known state. all the processor internal caches will be invalidated upon the reset. modified lines in the data cache are not written back. flush# and init are sampled when reset transitions from high to low to determine if tristate test mode will be entered or if bist will be run. scyc o the split cycle output is asserted during misaligned locked transfers to indicate that more than two cycles will be locked together. this signal is defined for locked cycles only. it is undefined for cycles which are not locked. smi# i the system management interrupt causes a system management interrupt request to be latched internally. when the latched smi# is recognized on an instruction boundary, the processor enters system management mode. smiact# o an active system management interrupt active output indicates that the processor is operating in system management mode. stpclk# i assertion of the stop clock input signifies a request to stop the internal clock of the pentium processor with voltage reduction technology thereby causing the core to consume less power. when the cpu recognizes stpclk#, the processor will stop execution on the next instruction boundary, unless superseded by a higher priority interrupt, and generate a stop grant acknowledge cycle. when stpclk# is asserted, the processor will still respond to external snoop requests. tck i the testability clock input provides the clocking function for the processor boundary scan in accordance with the ieee boundary scan interface (standard 1149.1). it is used to clock state information and data into and out of the processor during boundary scan. tdi i the test data input is a serial input for the test logic. tap instructions and data are shifted into the processor on the tdi pin on the rising edge of tck when the tap controller is in an appropriate state. tdo o the test data output is a serial output of the test logic. tap instructions and data are shifted out of the processor on the tdo pin on tck's falling edge when the tap controller is in an appropriate state. tms i the value of the test mode select input signal sampled at the rising edge of tck controls the sequence of tap controller state changes. trst# i when asserted, the test reset input allows the tap controller to be asynchronously initialized. v cc2 i these pins are the 2.45v power inputs to the core. mobile pentium ? processor with mmx? technology 29 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) table 5. quick pin reference (contd.) symbol type name and function vcc3 i these pins are the 3.3v power inputs to the i/o. vccdet# o v cc2 detect is used in flexible motherboard implementations to configure the voltage output set-point appropriately for the vcc2 inputs of the processor. 1 vss i these pins are the ground inputs. w/r# o write/read is one of the primary bus cycle definition pins. it is driven valid in the same clock as the ads# signal is asserted. w/r# distinguishes between write and read cycles. wb/wt# i the writeback/writethrough input allows a data cache line to be defined as writeback or writethrough on a line-by-line basis. as a result, it determines whether a cache line is initially in the s or e state in the data cache. note: 1. only in ppga package. mobile pentium ? processor with mmx? technology 30 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) 3.6. bus frequency core and bus frequencies can be set according to table 6 below. each mobile pentium processor with mmx technology specified to operate within a single bus-to-core ratio and a specific minimum to maximum bus frequency range (corresponding to a minimum to maximum core frequency range). operation in other bus-to-core ratios or outside the specified operating frequency range is not supported. table 6 . bus frequency selections bf1 bf0 bus/core ratio max bus/core frequency (mhz) min bus/core frequency (mhz) 0 0 2/5 60/150 66/166 30/75 33/83 0 1 1/3 2 n/a 2 n/a 2 1 0 1/2 1 66/133 33/66 1 1 reserved reserved reserved notes: 1. this is the default bus to core ratio for the mobile pentium ? processor with mmx? technology. if the bf pins are left floating, the processor will be configured for the 1/2 bus to core frequency ratio. 2. this bus ratio is currently not supported in mobile pentium processors. mobile pentium ? processor with mmx? technology 31 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) 3.7. pin reference tables table 7 . output pins 1 name active level when floated ads# low bus hold, boff# apchk# low be7#-be4# low bus hold, boff# breq high cache# low bus hold, boff# ferr# low hit# low hitm# 2 low hlda high ierr# low lock# low bus hold, boff# m/io#, d/c#, w/r# n/a bus hold, boff# pchk# low bp3-2, pm1/bp1, pm0/bp0 high prdy high pwt, pcd high bus hold, boff# scyc high bus hold, boff# smiact# low tdo n/a all states except shift-dr and shift-ir note: 1. all output and input/output pins are floated during tristate test mode (except tdo). 2. hitm# pin has an internal pull-up resistor. mobile pentium ? processor with mmx? technology 32 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) table 8 . input pins name active level synchronous/ asynchronous internal resistor qualified a20m# low asynchronous ahold high synchronous bf0 high synchronous/reset pull down bf1 high synchronous/reset pullup boff# low synchronous brdy# low synchronous pullup bus state t2,t12,t2p buschk# low synchronous pullup brdy# clk n/a eads# low synchronous ewbe# low synchronous brdy# flush# low asynchronous hold high synchronous ignne# low asynchronous init high asynchronous intr high asynchronous inv high synchronous eads# ken# low synchronous first brdy#/na# na# low synchronous bus state t2,td,t2p nmi high asynchronous pen# low synchronous brdy# r/s# n/a asynchronous pullup reset high asynchronous smi# low asynchronous pullup stpclk# low asynchronous pullup tck n/a pullup tdi n/a synchronous/tck pullup tck tms n/a synchronous/tck pullup tck trst# low asynchronous pullup wb/wt# n/a synchronous first brdy#/na# mobile pentium ? processor with mmx? technology 33 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) table 9 . input/output pins 1 name active level when floated qualified (when an input) internal resistor a31-a3 n/a address hold, bus hold, boff# eads# ap n/a address hold, bus hold, boff# eads# be3#-be0# low bus hold, boff# reset pulldown 2 d63-d0 n/a bus hold, boff# brdy# dp7-dp0 n/a bus hold, boff# brdy# notes: 1. all output and input/output pins are floated during tristate test mode (except tdo). 2. be3#-be0# have pulldowns during reset only. mobile pentium ? processor with mmx? technology 34 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) 3.8. pin grouping according to function table 10 organizes the pins with respect to their function. table 10 . pin functional grouping function pins clock clk initialization reset, init, bf[1:0] address bus a31-a3, be7# - be0# address mask a20m# data bus d63-d0 address parity ap, apchk# data parity dp7-dp0, pchk#, pen# internal parity error ierr# system error buschk# bus cycle definition m/io#, d/c#, w/r#, cache#, scyc, lock# bus control ads#, brdy#, na# page cacheability pcd, pwt cache control ken#, wb/wt# cache snooping/consistency ahold, eads#, hit#, hitm#, inv cache flush flush# write ordering ewbe# bus arbitration boff#, breq, hold, hlda interrupts intr, nmi floating-point error reporting ferr#, ignne# system management mode smi#, smiact# tap port tck, tms, tdi, tdo, trst# breakpoint/performance monitoring pm0/bp0, pm1/bp1, bp3-2 clock control stpclk# debugging r/s#, prdy mobile pentium ? processor with mmx? technology 35 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) 4.0. electrical specifications 4.1. maximum ratings the following values are stress ratings only. functional operation at the maximum ratings is not implied nor guaranteed. functional operating conditions are given in the ac and dc specification tables. extended exposure to the maximum ratings may affect device reliability. furthermore, although the mobile pentium processor with mmx technology contains protective circuitry to resist damage from electrostatic discharge (esd), always take precautions to avoid high static voltages or electric fields. case temperature under bias ......... - 65 c to 110 c storage temperature ....................... - 65 c to 150 c v cc3 supply voltage with respect to v ss .......................... - 0.5v to +4.6v v cc2 supply voltage with respect to v ss .......................... - 0.5v to +3.7v 3v only buffer dc input voltage ................................ ...... - 0.5v to v cc3 and +0.5v not to exceed v cc3 max warning stressing the device beyond the "absolute maximum ratings" may cause permanent damage. these are stress ratings only. operation beyond the "operating conditions" is not recommended and extended exposure beyond the "operating conditions" may affect device reliability. 4.2. dc specifications tables 11, 12 and 13 list the dc specifications which apply to the mobile pentium processor with mmx technology. the processor core operates at 2.45v internally while the i/o interface operates at 3.3v. 4.2.1. power sequencing there is no specific sequence required for powering up or powering down the v cc2 and v cc3 power supplies. however, for compatibility with future mobile processors, it is recommended that the v cc2 and v cc3 power supplies be either both on or both off within one second of each other. table 11 . v cc and t case specifications package t case supply min voltage max voltage voltage tolerance tcp 0 to 95oc v cc2 2.285v 2.665v 2.45v +0.215 / -0.165 v cc3 3.135v 3.465v 3.3v 5% ppga 0 to 85oc v cc2 2.285v 2.665v 2.45v +0.215 / -0.165 v cc3 3.135v 3.465v 3.3v 5% mobile pentium ? processor with mmx? technology 36 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) table 12 . 3.3v dc specifications 1 symbol parameter min max unit notes v il3 input low voltage -0.3 0.8 v ttl level 5 v ih3 input high voltage 2.0 v cc3 +0.3 v ttl level 4 v ol3 output low voltage 0.4 v ttl level 2 v oh3 output high voltage 2.4 v ttl level 3 notes: 1. see table 11 for v cc and t case assumptions. 2. parameter measured at -4 ma. 3. parameter measured at 3 ma. 4. parameter measured at nominal v cc3 which is 3.3v. 5. v il3,max for tck is 0.6v. table 13 . i cc specifications symbol parameter min max unit notes i cc2 power supply current 3.3 3.7 4.1 a a a 133 mhz 1 150 mhz 1 166mhz 1 i cc3 power supply current 0.4 0.37 0.4 a a a 133 mhz 1 150 mhz 1 166 mhz 1 note: 1. this value should be used for power supply design. it was determined using a worst case instruction mix an d maximum v cc . power supply transient response and decoupling capacitors must be sufficient to handle the instantaneous current changes occurring during transitions from stop clock to full active modes. mobile pentium ? processor with mmx? technology 37 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) table 14 . power dissipation requirements for thermal design parameter typical 1 max 2 unit frequency notes thermal design power n/a 7. 8 8.6 9.0 watts watts watts 133 mhz 150 mhz 166 mhz 6, 7 active power 4.4 5.0 5.5 n/a watts watts watts 133 mhz 150 mhz 166 mhz 5 stop grant / auto halt power n/a 0.86 0.93 1.00 watts watts watts 133 mhz 150 mhz 166 mhz 3 stop clock power 0.02 0.05 watts 133 mhz 150 mhz 166 mhz 4 notes: 1. this is the typical power dissipation in a system. this value is expected to be the average value that will be measured in a system using a typical device at v cc2 = 2.45v and v cc3 = 3.3v running typical applications. this value is highly dependent upon the specific system configuration. typical power specifications are not tested. 2. systems must be designed to thermally dissipate the maximum active power dissipation. it is determined using a worst- case instruction mix with v cc2 = 2.45v and v cc3 = 3.3v. the use of nominal v cc in this measurement takes into account the thermal time constant of the package. 3. stop grant/auto halt powerdown power dissipation is determined by asserting the stpclk# pin or executing the halt instruction. to achieve these values the tr12 bit21 must be set high. otherwise stop grant power will be higher: 133 mhz = 1.50w, 150 mhz = 1.60w, 166 mhz = 1.75w. tr12 bit21 is only supported in b-step and later. 4. maximum stop clock power dissipation is measured at 50 oc. at maximum temperature of 95 oc, processors will typically draw 90mw. 5. active power is the average power measured in a system using a typical device running typical applications under normal operating conditions at nominal v cc and room temperature. 6. for tdp (typ) refer to the mobile design consideration application note. 7. thermal design power is referenced at nominal dc supply voltage standard values as shown (v cc2 =2.45v, v cc2 =3.3v). system designers may choose to operate anywhere within the allowable v cc2 range (2.285v to 2.665v) as long as adequate decoupling is used to maintain the voltage tolerance within this range. common power supply voltages include: v cc2 =2.45v +0.215v / - - 0 .165v v cc2 =2.50v +/- 0 .165v actual tdp value will be higher as v cc2 nominal voltage is increased above the target value of 2.45v. likewise, tdp value will decrease as v cc2 is lowered below the target value of 2.45v . for example, a v cc2 of 2.5v will increase tdp(typ) by 300mw. mobile pentium ? processor with mmx? technology 38 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) table 15 . input and output characteristics symbol parameter min max unit notes c in input capacitance 15 pf 4 c o output capacitance 20 pf 4 c i/o i/o capacitance 25 pf 4 c clk clk input capacitance 15 pf 4 c tin test input capacitance 15 pf 4 c tout test output capacitance 20 pf 4 c tck test clock capacitance 15 pf 4 i li input leakage current 15 m a 0 mobile pentium ? processor with mmx? technology 40 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) table 16 . mobile pentium ? processor with mmx? technology ac specifications for 60-mhz bus operation see table 11 for v cc and t case specifications, c l = 0 pf symbol parameter min max unit figure notes frequency 30.0 60.0 mhz t 1a clk period 16.67 33.33 ns 5 t 1b clk period stability 250 ps 5 adjacent clocks, (1, 18) t 2 clk high time 4.0 ns 5 @2v, (1) t 3 clk low time 4.0 ns 5 @0.8v, (1) t 4 clk fall time 0.15 1.5 ns 5 (2.0v-0.8v), (1) t 5 clk rise time 0.15 1.5 ns 5 (0.8v-2.0v), (1) t 6a ads#, pwt, pcd, be0-7#, m/io#, d/c#, cache#, scyc, w/r# valid delay 1.0 7.0 ns 6 17 t 6b ap valid delay 1.0 8.5 ns 6 17 t 6c lock# valid delay 1.1 7.0 ns 6 17 t 6e a3-a31 valid delay 1.1 7.0 ns 6 17 mobile pentium ? processor with mmx? technology 41 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) table 16. mobile pentium ? processor with mmx? technology ac specifications for 60-mhz bus operation (contd.) see table 11 for v cc and t case specifications, c l = 0 pf symbol parameter min max unit figure notes t 7 ads#, ap, a3-a31, pwt, pcd, be0-7#, m/io#, d/c#, w/r#, cache#, scyc, lock# float delay 10.0 ns 7 1 t 8a apchk#, ierr#, ferr# valid delay 1.0 8.3 ns 6 4 t 8b pchk# valid delay 1.0 7.0 ns 6 4 t 9a breq, hlda valid delay 1.0 8.0 ns 6 4 t 9b smiact# valid delay 1.0 7.6 ns 6 4 t 10a hit# valid delay 1.0 8.0 ns 6 t 10b hitm# valid delay 1.1 6.0 ns 6 17 t 11a pm0-1, bp0-3 valid delay 1.0 10.0 ns 6 t 11b prdy valid delay 1.0 8.0 ns 6 t 12 d0-d63, dp0-7 write data valid delay 1.3 8.3 ns 6 t 13 d0-d63,dp0-3 write data float delay 10.0 ns 7 1 t 14 a5-a31 setup time 6.0 ns 8 t 15 a5-a31 hold time 1.0 ns 8 t 16a inv, ap setup time 5.0 ns 8 t 16b eads# setup time 5.5 ns 8 t 17 eads#, inv, ap hold time 1.0 ns 8 t 18a ken# setup time 5.0 ns 8 t 18b na#, wb/wt# setup time 4.5 ns 8 t 19 ken#, wb/wt#, na# hold time 1.0 ns 8 t 20 brdy# setup time 5.0 ns 8 t 21 brdy# hold time 1.0 ns 8 t 22 ahold, boff# setup time 5.5 ns 8 t 23 ahold, boff# hold time 1.0 ns 8 t 24 buschk#, ewbe#, hold, pen# setup time 5.0 ns 8 mobile pentium ? processor with mmx? technology 42 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) table 16. mobile pentium ? processor with mmx? technology ac specifications for 60-mhz bus operation (contd.) see table 11 for v cc and t case specifications, c l = 0 pf symbol parameter min max unit figure notes t 25 buschk#, ewbe#, pen# hold time 1.0 ns 8 t 25a hold hold time 1.5 ns 8 t 26 a20m#, intr, stpclk# setup time 5.0 ns 8 11,15 t 27 a20m#, intr, stpclk# hold time 1.0 ns 8 12 t 28 init, flush#, nmi, smi#, ignne# setup time 5.0 ns 8 11,12,16 t 29 init, flush#, nmi, smi#, ignne# hold time 1.0 ns 8 12 t 30 init, flush#, nmi, smi#, ignne# pulse width, async 2.0 clks 11,16 t 31 r/s# setup time 5.0 ns 8 9,11,16 t 32 r/s# hold time 1.0 ns 8 12 t 33 r/s# pulse width, async 2.0 clks 11,16 t 34 d0-d63, dp0-7 read data setup time 3.0 ns 8 t 35 d0-d63, dp0-7 read data hold time 1.5 ns 8 t 36 reset setup time 5.0 ns 9 8,9,11 t 37 reset hold time 1.0 ns 9 8,12 t 38 reset pulse width, v cc and clk stable 15.0 clks 9 8,16 t 39 reset active after v cc and clk stable 1.0 ms 9 power up t 40 reset configuration signals (init, flush#) setup time 5.0 ns 9 9,11,16 t 41 reset configuration signals (init, flush#) hold time 1.0 ns 9 12 t 42a reset configuration signals (init, flush#) setup time, async 2.0 clks 9 to reset falling edge (11) mobile pentium ? processor with mmx? technology 43 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) table 16. mobile pentium ? processor with mmx? technology ac specifications for 60-mhz bus operation (contd.) see table 11 for v cc and t case specifications, c l = 0 pf symbol parameter min max unit figure notes t 42b reset configuration signals (flush#, brdy#, init, buschk#) hold time, async 2.0 clks 9 to reset falling edge t 42c reset configuration signals (brdy#, buschk#) setup time, async 3.0 clks 9 to reset falling edge t 43a bf setup time to reset falling edge 1.0 ms 9 to reset falling edge (17) t 43b bf hold time to reset falling edge 2.0 clks 9 to reset falling edge (17) t 43c be4# setup time 2.0 clks 9 t 43d be4# hold time 2.0 clks 9 t 44 tck frequency ? 16.0 mhz t 45 tck period 62.5 ns 5 t 46 tck high time 25.0 ns 5 at 2v, (1) t 47 tck low time 25.0 ns 5 at 0.6v, (1) t 48 tck fall time 5.0 ns 5 (2.0v-0.6v), (1, 7, 8) t 49 tck rise time 5.0 ns 5 (0.6v-2.0v), (1, 5, 6) t 50 trst# pulse width 40.0 ns 11 (1), asynchronous t 51 tdi, tms setup time 5.0 ns 10 4 t 52 tdi, tms hold time 13.0 ns 10 4 t 53 tdo valid delay 3.0 20.0 ns 10 5 t 54 tdo float delay 25.0 ns 10 1,5 t 55 all non-test outputs valid delay 3.0 20.0 ns 10 3,5,16 t 56 all non-test outputs float delay 25.0 ns 10 1,3,5,16 t 57 all non-test inputs setup time 5.0 ns 10 3,4,16 t 58 all non-test inputs hold time 13.0 ns 10 3,4,16 mobile pentium ? processor with mmx? technology 44 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) notes for table 16: notes 2, 5, and 13 are general and apply to all standard ttl signals used with the pentium ? processor family. 1. not 100% tested. guaranteed by design/characterization. 2. ttl input test waveforms are assumed to be 0 to 3v transitions with 1v/ns rise and fall times. 3. non-test outputs and inputs are the normal output or input signals (besides tck, trst#, tdi, tdo, and tms). these timings correspond to the response of these signals due to boundary scan operations. 4. apchk#, ferr#, hlda, ierr#, lock#, and pchk# are glitch-free outputs. glitch-free signals monotonically transition without false transitions (i.e., glitches). 5. 0.3v/ns input rise/fall time 5v/ns. 6. referenced to tck rising edge. 7. referenced to tck falling edge. 8. 1 ns can be added to the maximum tck rise and fall times for every 10 mhz of frequency below 33 mhz. 9. during debugging, do not use the boundary scan timings (t 55-58 ). 10. this is a flight time specification, that includes both flight time and clock skew. the flight time is t he time from where the unloaded driver crosses 1.5v (50 percent of min v cc ), to where the receiver crosses the 1.5v level (50% of min v cc ). see figure 10. the minimum flight time minus the clock skew must be greater than zero. 11. setup time is required to guarantee recognition on a specific clock. 12. hold time is required to guarantee recognition on a specific clock. 13. all ttl timings are referenced from 1.5v. 14. to guarantee proper asynchronous recognition, the signal must have been de-asserted (inac tive) for a minimum of 2 clocks before being returned active and must meet the minimum pulse width. 15. this input may be driven asynchronously. 16. when driven asynchronously, reset, nmi, flush#, r/s#, init, and smi# must be de-asserted (inactive) for a minimum of 2 clocks before being returned active. 17. bf0 and bf1 should be strapped to v cc3 or v ss . 18. these signals are measured on the rising edge of adjacent clks at 1.5v. to ensure a 1:1 relationship between the amplitude of the input jitter and the internal and external clocks, the jitter frequency spectrum should not have any power spectrum peaking between 500 khz and 1/3 of the clk operating frequency. the amount of jitter present must be accounted for as a component of clk skew between devices. the internal clock generator requires a constant frequency clk input to within 250ps. therefore, the clk input cannot be changed dynamically. * each valid delay is specified for a 0 pf load. the system designer should use i/o buffer models to account for signal flight time delays. mobile pentium ? processor with mmx? technology 45 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) 4.3.5. ac timings for a 66-mhz bus the ac specifications given in table 17 consist of output delays, input setup requirements and input hold requirements for a 66 mhz external bus. all ac specifications (with the exception of those for the tap signals and apic signals) are relative to the rising edge of the clk input. all timings are referenced to 1.5v for both "0" and "1" logic levels unless otherwise specified. within the sampling window, a synchronous input must be stable for correct operation. each valid delay is specified for a 0 pf load. the system designer should use i/o buffer modeling to account for signal flight time delays. do not select a bus fraction and clock speed which will cause the processor to exceed its internal maximum frequency. table 17 . mobile pentium? processor with mmx? technology ac specifications for 66-mhz bus operation see table 11 for v cc and t case specifications, cl = 0 pf symbol parameter min max unit figure notes frequency 33.33 66.66 mhz t 1a clk period 15.0 30.0 ns 5 t 1b clk period stability 250 ps 5 adjacent clocks (1, 15) t 2 clk high time 4.0 ns 5 2v(1) t 3 clk low time 4.0 ns 5 0.8v(1) t 4 clk fall time 0.15 1.5 ns 5 (2.0v?0.8v)(1) t 5 clk rise time 0.15 1.5 ns 5 (0.8v?2.0v)(1) t 6a pwt, pcd, be0-7#, d/c#, cache#, scyc, w/r# valid delay 1.0 7.0 ns 6 t 6b ap valid delay 1.0 8.5 ns 6 t 6c lock# valid delay 1.1 7.0 ns 6 4 t 6d ads# valid delay 1.0 6.0 ns 6 t 6e a3-a31 valid delay 1.1 6.6 ns 6 t 6f m/io# valid delay 1.0 5.9 ns 6 t 7 ads#, adsc#, ap, a3-a31, pwt, pcd, be0-7#, m/io#, d/c#, w/r#, cache#, scyc, lock# float delay 10.0 ns 7 1 t 8a apchk#, ierr#, ferr# valid delay 1.0 8.3 ns 6 4 mobile pentium ? processor with mmx? technology 46 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) table 17. mobile pentium? processor with mmx? technology ac specifications for 66-mhz bus operation (contd.) see table 11 for v cc and t case specifications, c l = 0 pf symbol parameter min max unit figure notes t 8b pchk# valid delay 1.0 7.0 ns 6 4 t 9a breq valid delay 1.0 8.0 ns 6 4 t 9b smiact# valid delay 1.0 7.3 ns 6 4 t 9c hlda valid delay 1.0 6.8 ns 6 t 10a hit# valid delay 1.0 6.8 ns 6 t 10b hitm# valid delay 1.1 6.0 ns 6 t 11a pm0-1, bp0-3 valid delay 1.0 10.0 ns 6 t 11b prdy valid delay 1.0 8.0 ns 6 t 12 d0-d63, dp0-7 write data valid delay 1.3 8.0 ns 6 t 13 d0-d63, dp0-3 write data float delay 10.0 ns 7 1 t 14 a5-a31 setup time 6.0 ns 8 t 15 a5-a31 hold time 1.0 ns 8 t 16a inv, ap setup time 5.0 ns 8 t 16b eads# setup time 5.0 ns 8 t 17 eads#, inv, ap hold time 1.0 ns 8 t 18a ken# setup time 5.0 ns 8 t 18b na#, wb/wt# setup time 4.5 ns 8 t 19 ken#, wb/wt#, na# hold time 1.0 ns 8 t 20 brdy# setup time 5.0 ns 8 t 21 brdy# hold time 1.0 ns 8 t 22 ahold, boff# setup time 5.5 ns 8 t 23 ahold, boff# hold time 1.0 ns 8 t 24a buschk#, ewbe#, hold setup time 5.0 ns 8 t 24b pen# setup time 4.8 ns 8 t 25a buschk#, ewbe#, pen# hold time 1.0 ns 8 t 25b hold hold time 1.5 ns 8 mobile pentium ? processor with mmx? technology 47 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) table 17. mobile pentium? processor with mmx? technology ac specifications for 66-mhz bus operation (contd.) see table 11 for v cc and t case specifications, c l = 0 pf symbol parameter min max unit figure notes t 26 a20m#, intr, stpclk# setup time 5.0 ns 8 9,11 t 27 a20m#, intr, stpclk# hold time 1.0 ns 8 12 t 28 init, flush#, nmi, smi#, ignne# setup time 5.0 ns 8 9,11,16 t 29 init, flush#, nmi, smi#, ignne# hold time 1.0 ns 8 12 t 30 init, flush#, nmi, smi#, ignne# pulse width, async 2.0 clks 11,16 t 31 r/s# setup time 5.0 ns 8 9,11,16 t 32 r/s# hold time 1.0 ns 8 12 t 33 r/s# pulse width, async. 2.0 clks 11,16 t 34 d0-d63, dp0-7 read data setup time 2.8 ns 8 t 35 d0-d63, dp0-7 read data hold time 1.5 ns 8 t 36 reset setup time 5.0 ns 9 9,11 t 37 reset hold time 1.0 ns 9 12 t 38 reset pulse width, v cc & clk stable 15.0 clks 9 16 t 39 reset active after v cc & clk stable 1.0 ms 9 power up t 40 reset configuration signals (init, flush#) setup time 5.0 ns 9 9,11,16 t 41 reset configuration signals (init, flush#) hold time 1.0 ns 9 12 t 42a reset configuration signals (init, flush#) setup time, async. 2.0 clks 9 to reset falling edge(11) t 42b reset configuration signals (init, flush#,brdy#, buschk#) hold time, async. 2.0 clks 9 to reset falling edge t 42c reset configuration signals (brdy#, buschk#) setup time, async. 3.0 clks 9 to reset falling edge mobile pentium ? processor with mmx? technology 48 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) table 17. mobile pentium? processor with mmx? technology ac specifications for 66-mhz bus operation (contd.) see table 11 for v cc and t case specifications, c l = 0 pf symbol parameter min max unit figure notes t 42d reset configuration signal hold time, reset driven synchronously 1.0 ns 9 to reset falling edge(1) t 43a bf0, bf1 setup time 1.0 ms 9 to reset falling edge(17) t 43b bf0, bf1 hold time 2.0 clks to reset falling edge (17) t 43c be4# setup time 2.0 clks to reset falling edge t 43d be4# hold time 2.0 clks to reset falling edge t 44 tck frequency 16.0 mhz t 45 tck period 62.5 ns 5 t 46 tck high time 25.0 ns 5 2v(1) t 47 tck low time 25.0 ns 5 0.6v(1) t 48 tck fall time 5.0 ns 5 (2.0v?0.6v) (1, 5, 6) t 49 tck rise time 5.0 ns 5 (0.6v?2.0v) (1, 5, 6) t 50 trst# pulse width 40.0 ns 1 asynchronous(1) t 51 tdi, tms setup time 5.0 ns 10 4 t 52 tdi, tms hold time 13.0 ns 10 4 t 53 tdo valid delay 3.0 20.0 ns 10 5 t 54 tdo float delay 25.0 ns 10 1,5 t 55 all non-test outputs valid delay 3.0 20.0 ns 10 3,5,7 t 56 all non-test outputs float delay 25.0 ns 10 1,3,5,7 t 57 all non-test inputs setup time 5.0 ns 10 3,4,7 t 58 all non-test inputs hold time 13.0 ns 10 3,4,7 mobile pentium ? processor with mmx? technology 49 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) notes for table 17: notes 2, 5, and 13 are general and apply to all standard ttl signals used with the pentium ? processor family. 1. not 100% tested. guaranteed by design/characterization. 2. ttl input test waveforms are assumed to be 0 to 3v transitions with 1v/ns rise and fall times. 3. non-test outputs and inputs are the normal output or input signals (besides tck, trst#, tdi, tdo, and tms). these timings correspond to the response of these signals due to boundary scan operations. 4. apchk#, ferr#, hlda, ierr#, lock#, and pchk# are glitch-free outputs. glitch-fr ee signals monotonically transition without false transitions (i.e., glitches). 5. 0.3v/ns input rise/fall time 5v/ns. 6. referenced to tck rising edge. 7. referenced to tck falling edge. 8. 1 ns can be added to the maximum tck rise and fall times for every 10 mhz of frequency below 33 mhz. 9. during debugging, do not use the boundary scan timings (t 55-58 ). 10. this is a flight time specification, that includes both flight time and clock skew. the flight time is the time from where the unloaded driver crosses 1.5v (50% of min v cc ), to where the receiver crosses the 1.5v level (50% of min v cc ). see figure 10. the minimum flight time minus the clock skew must be greater than zero. 11. setup time is required to guarantee recognition on a specific clock. 12. hold time is required to guarantee recognition on a specific clock. 13. all ttl timings are referenced from 1.5v. 14. to guarantee proper asynchronous recognition, the signal must have been de-asserted (inactive) for a minimum of 2 clocks before being returned active and must meet the minimum pulse width. 15. this input may be driven asynchronously. 16. when driven asynchronously, reset, nmi, flush#, r/s#, init, and smi# must be de-asserted (inactive) for a minimum of 2 clocks before being returned active. 17. bf0 and bf1 should be strapped to v cc3 or v ss . 18. these signals are measured on the rising edge of adjacent clks at 1.5v. to ensure a 1:1 relationship between the amplitude of the input jitter and the internal and external clocks, the jitter frequency spectrum should not have any power spectrum peaking between 500 khz and 1/3 of the clk operating frequency. the amount of jitter present must be accounted for as a component of clk skew between devices. the internal clock generator requires a constant frequency clk input to within 250ps. therefore, the clk input cannot be changed dynamically. 19. each valid delay is specified for a 0 pf load. the system designer should use i/o buffer models to account for signal flight time delays. mobile pentium ? processor with mmx? technology 50 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) p p 0 0 5 1 t x t w t y t z t v t v t w t x t y t z = = = = = t5, t49 t 4 , t 4 8 t 2 , t 4 6 t 1 , t 4 5 t 3 , t 4 7 figure 5 . clock waveform p p 0 0 5 2 t s i g n a l v a l i d t m a x . x t m i n . x 1 . 5 v 1 . 5 v x = t 6 , t 8 , t 9 , t 1 0 , t 1 1 , t 1 2 figure 6 . valid delay timings mobile pentium ? processor with mmx? technology 51 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) t x = t 7 , t 1 3 t y = t 6 m i n , t 1 2 m i n pp0053 t x 1.5 v t y signal figure 7 . float delay timings p p 0 0 5 4 v a l i d t y t x 1 . 5 v c l k s i g n a l t x = t 1 4 , t 1 6 , t 1 8 , t 2 0 , t 2 2 , t 2 4 , t 2 6 , t 2 8 , t 3 1 , t 3 4 t y = t 1 5 , t 1 7 , t 1 9 , t 2 1 , t 2 3 , t 2 5 , t 2 7 , t 2 9 , t 3 2 , t 3 5 figure 8 . setup and hold timings mobile pentium ? processor with mmx? technology 52 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) p p 0 0 5 5 t x v a l i d 1 . 5 v 1 . 5 v t z t v t t t u t w t y c l k r e s e t c o n f i g t w = t 4 2 , t 4 3 a , t 4 3 c , t 4 3 e t x = t 4 3 b , t 4 3 d , t 4 3 f t y = t 3 8 , t 3 9 t z = t 3 6 t t = t 4 0 t u = t 4 1 t v = t 3 7 figure 9 . reset and configuration timings mobile pentium ? processor with mmx? technology 53 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) t r = t 5 7 t s = t 5 8 t u = t 5 4 t v = t 5 1 t w = t 5 2 t x = t 5 3 t y = t 5 5 t z = t 5 6 p p 0 0 5 6 t c k t d i t m s t d o o u t p u t s i g n a l s i n p u t s i g n a l s t v t w t x t y t r t s t u t z 1 . 5 v figure 10 . test timings t x = t 5 0 p p 0 0 5 7 1 . 5 v t x figure 11 . test reset timings mobile pentium ? processor with mmx? technology 54 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) 4.4. i/o buffer models this section describes the i/o buffer models of the mobile pentium processor with mmx technology. the first order i/o buffer model is a simplified representation of the complex input and output buffers used. figure 12 shows the structure of the input buffer model and figure 13 shows the output buffer model. tables 18 and 19 show the parameters used to specify these models. although simplified, these buffer models will accurately model flight time and signal quality. for these parameters, there is very little added accuracy in a complete transistor model. note: clk is not 5v tolerant. it is 3.3v tolerant only. the following model represents the input buffer model. figure 12 represents all of the input buffers. in addition to the input and output buffer parameters, input protection diode models are provided for added accuracy. these diodes have been optimized to provide esd protection and provide some level of clamping. although the diodes are not required for simulation, it may be more difficult to meet specifications without them. note, however, some signal quality specifications require that the diodes be removed from the input model. the series resistors (r s ) are a part of the diode model. remove these when removing the diodes from the input model. figure 13 shows the structure of the output buffer model. this model is used for all of the output buffers of the mobile pentium processor with mmx technology. mobile pentium ? processor with mmx? technology 55 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) figure 12 . input buffer model mobile pentium ? processor with mmx? technology 56 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) table 18 . parameters used in the specification of the first order input buffer model parameter description cin minimum and maximum value of the capacitance of the input buffer model lp minimum and maximum value of the package inductance cp minimum and maximum value of the package capacitance rs diode series resistance d1, d2 ideal diodes pp0061 figure 13 . first order output buffer model table 19 . parameters used in the specification of the first order output buffer model parameter description dv/dt minimum and maximum value of the rate of change of the open circuit voltage source used in the output buffer model r o minimum and maximum value of the output impedance of the output buffer model c o minimum and maximum value of the capacitance of the output buffer model l p minimum and maximum value of the package inductance c p minimum and maximum value of the package capacitance mobile pentium ? processor with mmx? technology 57 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) 4.4.1. buffer model parameters this section gives the parameters for each input, output and bidirectional buffers. the input, output and bidirectional buffer values of the processor are listed in table 21. these tables contain listings for all three types, do not get them confused during simulation. when a bidirectional pin is operating as an input, use the c in , c p and l p values; if it is operating as a driver, use all of the data parameters. please refer to table 20 for the groupings of the buffers. the input, output and bi-directional buffer?s values are listed below. these tables contain listings for all three types. when a bi-directional pin is operating as an input, just use the c in , c p and l p values, if it is operating as a driver use all the data parameters. table 20 . tcp signal to buffer type signals type driver buffer type receiver buffer type clk i er0 a20m#, ahold, bf, boff#, brdy#, buschk#, eads#, ewbe#, flush#, hold, ignne#, init, intr, inv, ken#, na#, nmi, pen#, r/s#, reset, smi#, stpclk#, tck, tdi, tms, trst#, wb/wt# i er1 apchk#, be[7:5]#, bp[3:2], breq, ferr#, ierr#, pcd, pchk#, pm0/bp0, pm1/bp1, prdy, pwt, smiact#, tdo o ed1 a[31:21], ap, be[4:0]#, cache#, d/c#, d[63:0], dp[8:0], hlda, lock#, m/io#, scyc i/o eb1 eb1 a[20:3], ads#, hitm#, w/r# i/o eb2 eb2 hit# i/o eb3 eb3 mobile pentium ? processor with mmx? technology 58 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) table 21 . input, output and bi-directional buffer model parameters for tcp buffer type tran si- tion dv/dt (v/nsec) r o (ohms) c p (pf) l p (nh) c o /c in (pf) min max min max min max min max min max er0 rising 0.23 0.23 8.61 8.61 0.8 1.2 (input) falling 0.23 0.23 8.61 8.61 0.8 1.2 er1 rising 0.16 0.38 5.75 10.22 0.8 1.2 (input) falling 0.16 0.38 5.75 10.22 0.8 1.2 ed1 rising 3/3.0 3.7/0.9 21.6 53.1 0.16 0.40 4.69 10.68 2.0 2.6 (output) falling 3/2.8 3.7/0.8 17.5 50.7 0.16 0.40 4.69 10.68 2.0 2.6 eb1 rising 3/3.0 3.7/0.9 21.6 53.1 0.16 0.36 4.53 9.21 2.0 2.6 (bidir) falling 3/2.8 3.7/0.8 17.5 50.7 0.16 0.36 4.53 9.21 2.0 2.6 eb2 rising 3/3.0 3.7/0.9 21.6 53.1 0.25 0.43 4.90 8.51 9.1 9.7 (bidir) falling 3/2.8 3.7/0.8 17.5 50.7 0.25 0.43 4.90 8.51 9.1 9.7 eb3 rising 3/3.0 3.7/0.9 21.6 53.1 0.25 0.25 4.97 4.97 3.3 3.9 (bidir) falling 3/2.8 3.7/0.8 17.5 50.7 0.25 0.25 4.97 4.97 3.3 3.9 mobile pentium ? processor with mmx? technology 59 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) table 22 . input, output and bi-directional buffer model parameters for ppga package buffer type tran si- tion dv/dt (v/nsec) r o (ohms) c p (pf) l p (nh) c o /c in (pf) min max min max min max min max min max er0 rising 3.0 5.0 4.0 7.2 0.8 1.2 (input) falling 3.0 5.0 4.0 7.2 0.8 1.2 er1 rising 1.1 6.1 4.7 15.3 0.8 1.2 (input) falling 1.1 6.1 4.7 15.3 0.8 1.2 ed1 rising 3/3.0 3.7/0.9 21.6 53.1 1.1 8.2 4.0 17.7 2.0 2.6 (output) falling 3/2.8 3.7/0.8 17.5 50.7 1.1 8.2 4.0 17.7 2.0 2.6 eb1 rising 3/3.0 3.7/0.9 21.6 53.1 1.3 8.7 4.0 18.7 2.0 2.6 (bidir) falling 3/2.8 3.7/0.8 17.5 50.7 1.3 8.7 4.0 18.7 2.0 2.6 eb2 rising 3/3.0 3.7/0.9 21.6 53.1 1.3 8.3 4.4 16.7 9.1 9.7 (bidir) falling 3/2.8 3.7/0.8 17.5 50.7 1.3 8.3 4.4 16.7 9.1 9.7 eb3 rising 3/3.0 3.7/0.9 21.6 53.1 1.9 7.5 9.9 14.3 3.3 3.9 (bidir) falling 3/2.8 3.7/0.8 17.5 50.7 1.9 7.5 9.9 14.3 3.3 3.9 table 23 . input buffer model parameters: d (diodes) symbol parameter d1 d2 is saturation current 1.4e-14a 2.78e-16a n emission coefficient 1.19 1.00 rs series resistance 6.5 ohms 6.5 ohms tt transit time 3 ns 6 ns vj pn potential 0.983v 0.967v cj0 zero bias pn capacitance 0.28 1 pf 0.365 pf m pn grading coefficient 0.385 0.376 mobile pentium ? processor with mmx? technology 60 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) 4.4.2. signal quality specifications signals driven by the system into the mobile pentium processor with mmx technology must meet signal quality specifications to guarantee that the components read data properly and to ensure that incoming signals do not affect the reliability of the component. there are two signal quality parameters: ringback and settling time. see section 4.4.2.3 for clk signal quality specification. 4.4.2.1. ringback excessive ringback can contribute to long-term reliability degradation of the mobile pentium processor with mmx technology, and can cause false signal detection. ringback is simulated at the input pin of a component using the input buffer model. ringback can be simulated with or without the diodes that are in the input buffer model. ringback is the absolute value of the maximum voltage at the receiving pin below v cc3 (or above v ss ) relative to v cc3 (or v ss ) level after the signal has reached its maximum voltage level. the input diodes are assumed present. maximum ringback on inputs = 0.8v (with diodes) if simulated without the input diodes, follow the maximum overshoot/undershoot specification. by meeting the overshoot/undershoot specification, the signal is guaranteed not to ringback excessively. if simulated with the diodes present in the input model, follow the maximum ringback specification. overshoot (undershoot) is the absolute value of the maximum voltage above v cc3 (below v ss ). the guideline assumes the absence of diodes on the input. maximum overshoot/undershoot on 3.3v mobile pentium processor mmx technology inputs (not clk) = 1.4v above v cc3 (without diodes). refer to section 4.4.2.3 for 3.3v clock specification. figure 14 . overshoot/undershoot and ringback guidelines mobile pentium ? processor with mmx? technology 61 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) 4.4.2.2. settling time the settling time is defined as the time a signal requires at the receiver to settle within 10 percent of v cc3 or v ss . settling time is the maximum time allowed for a signal to reach within 10 percent of its final value. most available simulation tools are unable to simulate settling time so that it accurately reflects silicon measurements. on a physical board, second-order effects and other effects serve to dampen the signal at the receiver. because of all these concerns, settling time is a recommendation or a tool for layout tuning and not a specification. settling time is simulated at the slow corner, to make sure that there is no impact on the flight times of the signals if the waveform has not settled. settling time may be simulated with the diodes included or excluded from the input buffer model. if diodes are included, settling time recommendation will be easier to meet. although simulated settling time has not shown good correlation with physical, measured settling time, settling time simulations can still be used as a tool to tune layouts. use the following procedure to verify board simulation and tuning with concerns for settling time. simulate settling time at the slow corner for a particular signal. if settling time violations occur (signal requires more than 12.5 ns. to settle to + 10 percent of its final value), simulate signal trace with d.c. diodes in place at the receiver pin. the d.c. diode behaves almost identically to the actual (non-linear) diode on the part as long as excessive overshoot does not occur. if settling time violations still occur, simulate flight times for five consecutive cycles for that particular signal. if flight time values are consistent over the five simulations, settling time should not be a concern. if however, flight times are not consistent over the five simulations, tuning of the layout is required. note that, for signals that are allocated two cycles for flight time, the recommended settling time is doubled. maximum settling time to within 10% of v ih or v il is: 12.5 ns at 66 mhz 14.2 ns at 60 m h z mobile pentium ? processor with mmx? technology 62 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) figure 15 . settling time 4.4.2.3. clk signal quality specifica tion the maximum overshoot, maximum undershoot, overshoot threshold duration, undershoot threshold duration, and maximum ringback specifications for clk are described below: maximum overshoot and maximum undershoot specification: the maximum overshoot of the clk signals should not exceed v cc3 ,nominal + 0.9v. the maximum undershoot of the clk signals must not drop below -0.9v. overshoot threshold duration specification: the overshoot threshold duration is defined as the sum of all time during which the clk signal is above v cc3 ,nominal + 0.5v within a single clock period. the overshoot threshold duration must not exceed 20 percent of the period. undershoot threshold duration specification: the undershoot threshold duration is defined as the sum of all time during which the clk signal is below -0.5v within a single clock period. the undershoot threshold duration must not exceed 20 percent of the period. maximum ringback specification: the maximum ringback of clk associated with their high states (overshoot) must not drop below v cc3 - 0.8v as shown in figure 17 . similarly, the maximum ringback of clk associated with their low states (undershoot) must not exceed 0.8v as shown in figure 19 . refer to table 24 and table 25 for a summary of the clock overshoot and undershoot specifications for the pentium processor with mmx technology. table 24 . overshoot specification summary specification name value units notes threshold level v cc 3,nominal + 0.5 v 1,2 maximum overshoot level v cc 3,nominal + 0.9 v 1,2 maximum threshold duration 20% of clock period above threshold voltage ns 2 mobile pentium ? processor with mmx? technology 63 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) table 24 . overshoot specification summary specification name value units notes maximum ringback v cc 3,nominal - 0.8 v 1,2 notes: 1. v cc3 , nominal refers to the voltage measured at the bottom side of the v cc 3 pins. see section 7.1.2.1.1 for details. 2. see figures 16 and 17 . table 25 . undershoot specification summary specification name value units notes threshold level -0.5 v 1 minimum undershoot level -0.9 v 1 maximum threshold duration 20% of clock period below threshold voltage ns 1 maximum ringback 0.8 v 1 note: 1. see figures 18 and figure 19 . mobile pentium ? processor with mmx? technology 64 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) clock signal measurement methodology : the waveform of the clock signals should be measured at the bottom side of the processor pins using an oscilloscope with a 3 db bandwidth of at least 20 mhz (100 ms/s digital sampling rate). there should be a short isolation ground lead attached to a processor pin on the bottom side of the board. an 1 mohm probe with loading of less than 1 pf (e.g., tektronics 6243 or tektronics 6245) is recommended. the measurement should be taken at the clk (ak18) pin and its nearest v ss pin (am18). maximum overshoot, maximum undershoot and maximum ringback specifications: the display should show continuous sampling (e.g., infinite persistence) of the waveform at 500 mv/div and 5 ns/div for a recommended duration of approximately five seconds. adjust the vertical position to measure the maximum overshoot and associated ringback with the largest possible granularity. similarly, readjust the vertical position to measure the maximum undershoot and associated ringback. there is no allowance for crossing the maximum overshoot, maximum undershoot or maximum ringback specifications. overshoot threshold duration specification: a snapshot of the clock signal should be taken at 500 mv/div and 500 ps/div. adjust the vertical position and horizontal offset position to view the threshold duration. the overshoot threshold duration is defined as the sum of all time during which the clock signal is above v cc3 ,nominal + 0.5v within a single clock period. the overshoot threshold duration must not exceed 20 percent of the period. undershoot threshold duration specification: a snapshot of the clock signal should be taken at 500 mv/div and 500 ps/div. adjust the vertical position and horizontal offset position to view the threshold duration. the undershoot threshold duration is defined as the sum of all time during which the clock signal is below - 0.5v within a single clock period. the undershoot threshold duration must not exceed 20 percent of the period. these overshoot and undershoot specifications are illustrated graphically in figures 16 through 19 . overshoot threshold level maximum overshoot level overshoot threshold duration v cc3 , nominal figure 16 . maximum overshoot level, overshoot threshold level, and overshoot threshold duration mobile pentium ? processor with mmx? technology 65 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) maximum ringback v cc3 , nominal figure 17 . maximum ringback associated with the signal high state maximum undershoot level undershoot threshold level undershoot threshold duration v ss ,nominal figure 18 . maximum undershoot level, undershoot threshold level, and undershoot threshold duration mobile pentium ? processor with mmx? technology 66 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) maximum ringback v ss , nominal figure 19 . maximum ringback associated with the signal low state 5.0. mechanical specifications today's portable computers face the challenge of meeting desktop performance in an environment that is constrained by thermal, mechanical and electrical design considerations. these considerations have driven the development and implementation of intel?s tape carrier package (tcp). the intel tcp has been designed to offer a high pin count, low profile, reduced footprint package with uncompromised thermal and electrical performance. intel continues to provide packaging solutions that meet our rigorous criteria for quality and performance. key features of the tcp include: surface mount technology design, lead pitch of 0.25 mm, polyimide body size of 24 mm and polyimide up for pick-and- place handling. tcp components are shipped with the leads flat in slide carriers, and are designed to be excised and lead formed at the customer manufacturing site. recommendations for the manufacture of this package are included in the 1996 packaging databook (order number 240800) . figure 20 shows a cross-section view of the tcp as mounted on the printed circuit board. figures 21 and 22 show the tcp as shipped in its slide carrier, and key dimensions of the carrier and package. figure 23 shows a cross-section detail of the package. figure 24 shows an enlarged view of the outer lead bond area of the package. mobile pentium ? processor with mmx? technology 67 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) 5.1. tcp mechanical diagrams encapsulant polyimide support ring tab lead (ofc copper) polyimide keeper bar gold bump thermally conductive adhesive thermal vias ground plane 1/2 cross-section pcb full cross-section note: sketches not to scale pcb pcb 255703 figure 20 . cross-sectional view of the mounted tcp mobile pentium ? processor with mmx? technology 68 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) 255705 figure 21 . one tcp site in carrier (bottom view of die) mobile pentium ? processor with mmx? technology 69 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) 255706 figure 22 . one tcp site in carrier (top view of die) mobile pentium ? processor with mmx? technology 70 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) 255707 figure 23 . one tcp site (cross-sectional detail) mobile pentium ? processor with mmx? technology 71 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) 255708 figure 24 . outer lead bond (olb) window detail mobile pentium ? processor with mmx? technology 72 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) table 26 . tcp key dimensions symbol description dimension n leadcount 320 leads w tape width 48.18 0.12 l site length (43.94) reference only t test pad pitch 0.40 nominal e1 outer lead pitch 0.25 nominal b outer lead width 0.10 0.01 d1,e1 package body size 24.0 0.1 a2 package height 0.597 0.030 dl die length 12.23772 dw die width 10.57910 lt lead thickness 0.025 mm el encap length 13.46* ew encap width 11.71* notes: dimensions are in millimeters unless otherwise noted. dimensions in parentheses are for reference only. table 27 . mounted tcp dimensions symbol description dimension a package height 0.75 maximum d, e terminal dimension 29.5 nominal wt package weight 0.5 g maximum note: dimensions are in millimeters unless otherwise noted. package terminal dimension (lead tip-to-lead tip) assumes the use of a keeper bar. mobile pentium ? processor with mmx? technology 73 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) 5.2. plastic pin grid array (ppga) the mobile pentium processor with mmx technology is also available in a 296-pin plastic pin grid array ( p pga) package. the pins are arranged in a 37 by 37 matrix and the package dimensions are 1.95" x 1.95" (4.95 cm x 4.95 cm). figures 25 and 26 show ppga package dimensions. d d1 d3 d3 d1 d seating plane l 1.65 ref 2.29 1.52 ref. 45 index chamfer (index corner) a a1 a2 e1 s1 s1 ? b pin c3 bottom view (pin side up) side view figure 25 . mobile pentium? processor with mmx? technology ppga package dimensions bottom and side view mobile pentium ? processor with mmx? technology 74 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) figure 26 . mobile pentium? processor with mmx? technology ppga package dimensions table 28 . ppga package dimensions 296-pin plastic pin grid array package millimeters inches symbol min max min max a 2.62 2.97 0.103 0.117 a1 0.69 0.84 0.027 0.033 a2 3.31 3.81 0.130 0.150 b 0.43 0.51 0.017 0.020 d 49.28 49.78 1.940 1.960 d1 45.59 45.85 1.795 1.805 e1 2.29 2.79 0.090 0.110 l 3.05 3.30 0.120 0.130 n 296 296 s1 1.52 2.54 0.060 0.100 mobile pentium ? processor with mmx? technology 75 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) 6.0. thermal specifications the mobile pentium processor with mmx technology is specified for proper operation when the case temperature, t case (t c ), for tcp is within the specified range of 0 c to 95 c and within the specified range of 0 c to 85 c for ppga. 6.1. measuring thermal values for tcp to verify that the proper t c (case temperature) is maintained, it should be measured at the center of the package top surface (encapsulant). to minimize any measurement errors, the following techniques are recommended: use 36 gauge or finer diameter k, t, or j type thermocouples. intel's laboratory testing was done using a thermocouple made by omega (part number: 5tc-ttk-36-36). attach the thermocouple bead or junction to the center of the package top surface using highly thermally conductive cements. intel's laboratory testing was done by using omega bond (part number: ob-100). the thermocouple should be attached at a 90 angle as shown in figure 27 . 6.1.1. tcp thermal equations for the tcp mobile pentium processor with mmx technology, an ambient temperature (t a ) is not specified directly. the only requirement is that the case temperature (t c ) is met. the ambient temperature can be calculated from the following equations: [ ] t t p t t p t t p t t p j c jc a j ja a c ca c a ja jc ca ja jc = + = - = - = + - = - q q q q q q q q ( ) where, t a and t c are ambient and case temperatures ( c) q ca = case-to-ambient thermal resistance ( c/w) q ja = junction-to-ambient thermal resistance ( c/w) q jc = junction-to-case thermal resistance ( c/w) p = maximum power consumption (watts) p (maximum power consumption) is specified in section 3.1. 6.1.2. tcp thermal characteristics the primary heat transfer path from the die of the tcp is through the back side of the die and into the pc board. there are two thermal paths traveling from the pc board to the ambient air. one is the spread of heat within the board and the dissipation of heat by the board to the ambient air. the other is the transfer of heat through the board and to the opposite side where thermal enhancements (e.g., heat sinks, pipes) are attached. solder-side heat sinking, compared to tcp component-side heat sinking, is the preferred method due to reduced risk of die damage, easier mechanical implementation and larger surface area for attachment. however, component-side heat sinking is possible. the design requirements in a component-side thermal solution are: no direct loading of inner lead bonds on the tcp, a maximum force of 4.5 kgf on the center of a clean tcp, no direct loading of the tab tape or outer lead bonds and controlled board deflection. 6.1.3. tcp pc board enhancements copper planes, thermal pads, and vias are design options that can be used to improve heat transfer from the pc board to the ambient air. tables 28 and 29 present thermal resistance data for copper plane thickness and via effects. it should be noted that although thicker copper planes will reduce the q ca of a system without any thermal enhancements, they have less effect on the q ca of a system with thermal enhancements. however, placing vias under the die will reduce the q ca of a system with and without thermal enhancements. mobile pentium ? processor with mmx? technology 76 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) 255704 figure 27 . technique for measuring case temperature (t c ) on tcp table 29 . tcp thermal resistance vs. copper plane thickness with and without enhancements copper plane thickness* q ca (c/watt) no enhancements q ca (c/watt) with heat pipe and al plates 1 oz. cu 18 7.8 3 oz. cu 14 7.8 note: *225 vias underneath the die table 30 . tcp thermal resistance vs. thermal vias underneath the die number of vias under the die* q ca (c/watt) no enhancements 0 15 144 13 note: *3 oz. copper planes in tet boards 6.1.3.1. tcp standard test board configuration all tape carrier package (tcp) thermal measurements familiarity provided in the following tables were taken with the component soldered to a 2" x 2" test board outline. this six-layer board contains 225 vias in the die attach pad which are connected to two 3 oz. copper planes located at layers two and five. for the tcp, the vias in the die attach pad should be connected without thermal reliefs to the ground plane(s). the die is attached to the die attach pad using a thermally conductive adhesive. this test board was designed to optimize the heat spreading into the board and the heat transfer through to the opposite side of the board. note thermal resistance values should be used as guidelines only, and are highly system dependent. final system verification should always refer to the case temperature specification. mobile pentium ? processor with mmx? technology 77 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) table 31 . tcp thermal resistance without enhancements q jc (c/watt) q ca (c/watt) thermal resistance without enhancements 0.8 14 table 32 . tcp thermal resistance with enhancements (without airflow) thermal enhancements q ca (c/w) notes heat sink 11.7 1.2" 1.2" .35" al plate 8.7 4" 4" .030" al plate with heat pipe 7.8 0.3? 1" 4" heat pipe 4?x4?x0.3? al plate table 33 . tcp thermal resistance with enhancements (with airflow) thermal enhancements q ca (c/w) notes heat sink with fan @ 1.7 cfm 5.0 1.2" 1.2" .35" hs 1" 1" .4" fan heat sink with airflow @ 400 lfm 5.1 1.2?x1.2?x.35? hs heat sink with airflow @ 600 lfm 4.3 1.2" 1.2" .35" hs notes: hs = heat sink lfm = linear feet/minute cfm = cubic feet/minute 6.2. measuring thermal values for ppga to verify that the proper t c (case temperature) is maintained, it should be measured at the center of the package top surface (opposite of the pins). the measurement is made in the same way with or without a heat sink attached. when a heat sink is attached, a hole (smaller than 0.150" diameter) should be drilled through the heat sink to allow probing the center of the package. to minimize the measurement errors, it is recommended to use the following approach: use 36-gauge or finer diameter k, t, or j type thermocouples. the laboratory testing was done using a thermocouple made by omega (part number: 5tc-ttk-36-36). attach the thermocouple bead or junction to the center of the package top surface using high thermal conductivity cements. the laboratory testing was done by using omega bond (part number: ob-100). the thermocouple should be attached at a 90 -degree angle as shown in figure 28 . the hole size shou ld be smaller than 0.150? in diameter. make sure there is no contact between thermocouple cement and heat sink base. the contact will affect the thermocouple reading. mobile pentium ? processor with mmx? technology 78 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) 6.2.1. thermal equations and data for the mobile pentium processor with mmx technology ppga package, an ambient temperature, t a (air temperature around the processor), is not specified directly. the only restriction is that t c is met. to calculate t a values, the following equations may be used: t a = t c - (p * q ca ) q ca = q ja - q jc where: t a and t c = ambient and case temperature. (oc) q ca = case-to-ambient thermal resistance. (oc/watt) q ja = junction-to-ambient thermal resistance. (oc/watt) q jc = junction-to-case thermal resistance. (oc/watt) p = maximum power consumption (watt) table 34 lists the q jc and q ca values for the mobile pentium processor with mmx technology ppga package with passive heat sinks. q jc is thermal resistance from die to package case . q jc values shown in these tables are typical values. the actual q jc values depend on actual thermal conductivity and process of die attach. q ca is thermal resistance from package case to the ambient. q ca values shown in these tables are typical values. the actual q ca values depend on the heat sink design, interface between heat sink and package, the air flow in the system, and thermal interactions between cpu and surrounding components through pcb and the ambient. figure 29 shows table 34 in graphical format. ppga 199713 figure 28 . technique for measuring t c on ppga packages mobile pentium ? processor with mmx? technology 79 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) table 34 . thermal resistances for ppga packages heat sink height in q ca (c/watt) vs. laminar airflow (linear ft/min) inches q jc (c/watt) 0 100 200 400 600 800 0.25" 0.4 8.9 7.8 6.4 4.3 3.4 2.8 0.35" 0.4 8.6 7.3 5.8 3.8 3.1 2.6 0.45" 0.4 8.2 6.8 5.1 3.4 2.7 2.3 0.55" 0.4 7.9 6.3 4.5 3.0 2.4 2.1 0.65" 0.4 7.5 5.8 4.1 2.8 2.2 1.9 0.80" 0.4 6.8 5.1 3.7 2.6 2.0 1.8 1.00" 0.4 6.1 4.5 3.4 2.4 1.9 1.6 1.20" 0.4 5.7 4.1 3.1 2.2 1.8 1.6 1.40" 0.4 5.2 3.7 2.8 2.0 1.7 1.5 none 1.2 12.9 12.2 11.2 7.7 6.3 5.4 notes: heat sinks are omni directional pin aluminum alloy. features were based on standard extrusion practices for a given height pin size ranged from 50 to 129 mils pin spacing ranged from 93 to 175 mils based thickness ranged from 79 to 200 mils heat sink attach was 0.005? of thermal grease. attach thickness of 0.002? will improve performance approximately 0.3 o c/watt mobile pentium ? processor with mmx? technology 80 5/14/97 8:29 am 243292_3.doc intel confidential (until publication date) 0 1 2 3 4 5 6 7 8 9 10 0.2 0.4 0.6 0.8 1.0 1.2 1.4 heat sink height [in] theta ca [c/w] 0 100 200 400 600 800 air flow rate [lfm] 199721 figure 29 . thermal resistance vs. heatsink height, ppga packages |
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